公开(公告)号：US20050275085A1

公开(公告)日：2005-12-15

申请号：US11140578

申请日：2005-05-27

申请人： Axel Brintzinger ,  Octavio Trovarelli ,  Ingo Uhlendorf ,  Stefan Ruckmich ,  David Wallis ,  Fritz Uhlendorf ,  Helga Uhlendorf

发明人： Axel Brintzinger ,  Octavio Trovarelli ,  Ingo Uhlendorf ,  Stefan Ruckmich ,  David Wallis ,  Fritz Uhlendorf ,  Helga Uhlendorf

IPC分类号： H01L23/12 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5222 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor (10) being respectively arranged between adjacent conductors of the redistribution routing (1) and/or at least a second passivation (7) with a lower dielectric constant of a preferred “cold dielectric” being arranged between the redistribution routing (1) and the first passivation (2) on the active region of the chip (3).

摘要翻译： 一种布置减少了芯片上的电串扰，特别是在再分配路由的相邻导体之间和/或芯片上的第一钝化上的再分配布线之间以及芯片的金属化之间的电串扰。 在一个方面，该布置减少了芯片上的再分配布线与其金属化之间的串扰，并且可以在前端简单且独立地实现。 这通过分别布置在再分配路由（1）的相邻导体和/或至少第二钝化层（7）之间的至少一个额外的导体（10）来实现，其中优选的“冷电介质”的较低介电常数被布置 在芯片（3）的有源区域上的再分配路由（1）和第一钝化（2）之间。