公开(公告)号：US07487398B2

公开(公告)日：2009-02-03

申请号：US11300423

申请日：2005-12-15

申请人： Ayman G. Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn W. Merrell

发明人： Ayman G. Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn W. Merrell

IPC分类号： G06F11/00

CPC分类号： G06F11/24 ,  G06F11/27

摘要： Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

摘要翻译： 通过在总线上产生骚扰事务来测试计算机系统的元素。 在总线上检测到第一个事务。 第一个事务包括对第一个地址的第一个数据请求。 响应并且基于检测到第一地址，生成第二数据请求到第二地址。 第二个数据请求作为第二个事务在总线上发出，而总线上第一个事务处于待处理状态。

公开(公告)号：US07032134B2

公开(公告)日：2006-04-18

申请号：US09818788

申请日：2001-03-28

申请人： Ayman G. Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn W. Merrell

发明人： Ayman G. Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn W. Merrell

IPC分类号： G06F11/22

CPC分类号： G06F11/24 ,  G06F11/27

摘要： A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.

公开(公告)号：US20060107120A1

公开(公告)日：2006-05-18

申请号：US11300423

申请日：2005-12-15

申请人： Ayman Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn Merrell

发明人： Ayman Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn Merrell

IPC分类号： G06F11/00

CPC分类号： G06F11/24 ,  G06F11/27

摘要： Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

公开(公告)号：US20140359640A1

公开(公告)日：2014-12-04

申请号：US13997734

申请日：2011-12-30

申请人： Cameron McNairy ,  Don Soltis

发明人： Cameron McNairy ,  Don Soltis

IPC分类号： G06F9/54

CPC分类号： G06F9/45541 ,  G06F9/441 ,  G06F9/542 ,  G06F12/0893

摘要： Embodiments of a system and method for triggering an event in a hardware abstraction layer (HAL) are generally described herein. In some embodiments, the HAL can include unarchitected hardware or software that can be used to, for example, facilitate instruction emulation and debug; enable protection of model specific resources, instructions, and behaviors; redirect, resteer, or substitute instructions; and provide a framework for additional capabilities and features.

摘要翻译： 在此通常描述用于触发硬件抽象层（HAL）中的事件的系统和方法的实施例。 在一些实施例中，HAL可以包括未被归档的硬件或软件，其可以用于例如便于指令仿真和调试; 使模型具体资源，指令和行为得以保护; 重定向，修复或替代说明; 并为其他功能和功能提供框架。

公开(公告)号：US20140019814A1

公开(公告)日：2014-01-16

申请号：US13992379

申请日：2011-12-21

申请人： Cameron McNairy ,  David Heckman ,  Jenna Mayfield ,  Scott Hoyt

发明人： Cameron McNairy ,  David Heckman ,  Jenna Mayfield ,  Scott Hoyt

IPC分类号： G06F11/10

CPC分类号： G06F11/0766 ,  G06F11/0781 ,  G06F11/079 ,  G06F11/2215 ,  G06F11/2268 ,  G06F11/263

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing an error framework for a microprocessor and for a system having such a microprocessor. The error framework may alternatively be implemented by a hardware component, such as a peripheral device for integration into a system. In one embodiment, an error framework of a microprocessor or a hardware component includes an error detection unit to capture an error within the hardware component; a state detection unit to capture error context information when the error is detected within the hardware component; an error event definition unit to define a unique error event representing a combination of the error and the error context information; and a configuration unit to define an error event response based on the unique error event. The error context information may include, for example, a known state of a system at the time the error occurs or a known state of the hardware component or microprocessor within which the error is detected at the time the error occurs.

摘要翻译： 根据本文公开的实施例，提供了用于实现微处理器和具有这种微处理器的系统的错误框架的方法，系统，机制，技术和装置。 错误框架可以替代地由诸如用于集成到系统中的外围设备的硬件组件来实现。 在一个实施例中，微处理器或硬件组件的错误框架包括用于捕获硬件组件内的错误的错误检测单元; 状态检测单元，用于当在所述硬件组件内检测到所述错误时捕获错误上下文信息; 错误事件定义单元，用于定义表示所述错误和所述错误上下文信息的组合的唯一错误事件; 以及基于唯一错误事件定义错误事件响应的配置单元。 错误上下文信息可以包括例如在发生错误时系统的已知状态或在发生错误时检测到错误的硬件组件或微处理器的已知状态。

公开(公告)号：US09495233B2

公开(公告)日：2016-11-15

申请号：US13992379

申请日：2011-12-21

申请人： Cameron McNairy ,  David Heckman ,  Jenna Mayfield ,  Scott Hoyt

发明人： Cameron McNairy ,  David Heckman ,  Jenna Mayfield ,  Scott Hoyt

IPC分类号： G06F11/07 ,  G06F11/263 ,  G06F11/22

CPC分类号： G06F11/0766 ,  G06F11/0781 ,  G06F11/079 ,  G06F11/2215 ,  G06F11/2268 ,  G06F11/263

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing an error framework for a microprocessor and for a system having such a microprocessor. The error framework may alternatively be implemented by a hardware component, such as a peripheral device for integration into a system. In one embodiment, an error framework of a microprocessor or a hardware component includes an error detection unit to capture an error within the hardware component; a state detection unit to capture error context information when the error is detected within the hardware component; an error event definition unit to define a unique error event representing a combination of the error and the error context information; and a configuration unit to define an error event response based on the unique error event. The error context information may include, for example, a known state of a system at the time the error occurs or a known state of the hardware component or microprocessor within which the error is detected at the time the error occurs.

摘要翻译： 根据本文公开的实施例，提供了用于实现微处理器和具有这种微处理器的系统的错误框架的方法，系统，机制，技术和装置。 错误框架可以替代地由诸如用于集成到系统中的外围设备的硬件组件来实现。 在一个实施例中，微处理器或硬件组件的错误框架包括用于捕获硬件组件内的错误的错误检测单元; 状态检测单元，用于当在所述硬件组件内检测到所述错误时捕获错误上下文信息; 错误事件定义单元，用于定义表示所述错误和所述错误上下文信息的组合的唯一错误事件; 以及基于唯一错误事件定义错误事件响应的配置单元。 错误上下文信息可以包括例如在发生错误时系统的已知状态或在发生错误时检测到错误的硬件组件或微处理器的已知状态。

公开(公告)号：US09483293B2

公开(公告)日：2016-11-01

申请号：US13997734

申请日：2011-12-30

申请人： Cameron McNairy ,  Don Soltis

发明人： Cameron McNairy ,  Don Soltis

IPC分类号： G06F9/455 ,  G06F9/54 ,  G06F12/08 ,  G06F9/44

CPC分类号： G06F9/45541 ,  G06F9/441 ,  G06F9/542 ,  G06F12/0893

摘要： Embodiments of a system and method for triggering an event in a hardware abstraction layer (HAL) are generally described herein. In some embodiments, the HAL can include unarchitected hardware or software that can be used to, for example, facilitate instruction emulation and debug; enable protection of model specific resources, instructions, and behaviors; redirect, resteer, or substitute instructions; and provide a framework for additional capabilities and features.

摘要翻译： 在此通常描述用于触发硬件抽象层（HAL）中的事件的系统和方法的实施例。 在一些实施例中，HAL可以包括未被归档的硬件或软件，其可以用于例如便于指令仿真和调试; 使模型具体资源，指令和行为得以保护; 重定向，修复或替代说明; 并为其他功能和功能提供框架。