公开(公告)号：US20190045675A1

公开(公告)日：2019-02-07

申请号：US15668017

申请日：2017-08-03

Applicant: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Inventor： Bin Li ,  Lloyd Brown ,  Patrick Fleming ,  Jason F. Ross

IPC: H05K9/00 ,  H04J3/04

Abstract: A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.

公开(公告)号：US09183332B2

公开(公告)日：2015-11-10

申请号：US14251267

申请日：2014-04-11

Applicant: BAE Systems Information And Electronic Systems Integration Inc.

Inventor： Richard Ferguson ,  Lloyd Brown

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.

Abstract translation: 提出了一种用于在设计的一小部分上运行香料的自动化方式的系统和方法。 该系统包括一个子电路网表生成处理器和一个模拟仿真处理器。 子电路网表生成处理器至少部分地基于HDL网表，寄生电容数据库和跟踪规则来生成子电路网表。 子电路网表包含比整个设计的HDL网表少得多的路径，以便其模拟时间更快。 模拟仿真处理器至少部分地基于动态输入产生子电路网表的模拟仿真结果。

公开(公告)号：US20140325460A1

公开(公告)日：2014-10-30

申请号：US14251267

申请日：2014-04-11

Applicant: BAE Systems Information And Electronic Systems Integration Inc.

Inventor： Richard Ferguson ,  Lloyd Brown

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.

Abstract translation: 提出了一种用于在设计的一小部分上运行香料的自动化方式的系统和方法。 该系统包括一个子电路网表生成处理器和一个模拟仿真处理器。 子电路网表生成处理器至少部分地基于HDL网表，寄生电容数据库和跟踪规则来生成子电路网表。 子电路网表包含比整个设计的HDL网表少得多的路径，以便其模拟时间更快。 模拟仿真处理器至少部分地基于动态输入产生子电路网表的模拟仿真结果。