公开(公告)号：US20040017233A1

公开(公告)日：2004-01-29

申请号：US10201045

申请日：2002-07-23

Applicant: BAE Systems, Information and Electronic Systems Integration, Inc.

Inventor： Neil E. Wood

IPC: H03K021/00

CPC classification number: H03K5/15093 ,  H03K19/0033 ,  H03K21/40

Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

Abstract translation: 公开了一种单事件不安免疫分频器电路。 单事件不安免疫分频器电路包括双路移位寄存器，双路多路复用器和求和电路。 双通道移位寄存器具有时钟输入，一个信号输入对和多个信号输出对。 双路多路复用器具有多个信号输入对和一个输出对。 双路多路复用器的信号输入对分别连接到双输入移位寄存器的信号输出对。 双路多路复用器选择双路移位寄存器的信号输出对之一，以反馈到双路移位寄存器的信号输入对。 然后，求和电路对双路移位寄存器的信号输入对进行求和，以产生作为双路移位寄存器的时钟输入端的输入时钟信号频率的一部分的输出时钟信号。