公开(公告)号：US20240079947A1

公开(公告)日：2024-03-07

申请号：US18241739

申请日：2023-09-01

Applicant: BATTELLE MEMORIAL INSTITUTE

Inventor： Wei Du ,  Yuan Liu ,  Quan Nguyen ,  Sheik Mohammad Mohiuddin

IPC: H02M1/00 ,  H02M1/32 ,  H02M7/5395

CPC classification number: H02M1/0019 ,  H02M1/0009 ,  H02M1/0012 ,  H02M1/32 ,  H02M7/5395

Abstract: This document describes systems and techniques for a current-limiting control strategy for single-loop droop-controlled grid-forming inverters. In aspects, a hysteresis module is configured to compare an output current detected across one or more transistors in an inverter controlled by the single-loop droop converter with a specified maximum current and to generate an overcurrent signal. The overcurrent signal presents a fault signal responsive to the output current exceeding the specified maximum current. A logic array is configured to logically combine gate control signals generated by the single-loop droop controller to selectively direct the one or more transistors to allow the output current to flow therethrough with the overcurrent signal to present modified gate control signals to the one or more transistors. The logic array is configured to replace one or more of the gate control signals in the modified gate control signals with a gate disable signal responsive to the overcurrent signal presenting the fault signal.