公开(公告)号：US3825827A

公开(公告)日：1974-07-23

申请号：US24364972

申请日：1972-04-13

Applicant: BENDIX CORP

Inventor： TUMBUSH G

IPC: G01D1/18 ,  G01D7/00 ,  G01R13/40 ,  G01R17/00 ,  G09F9/00 ,  G09F9/30 ,  G09F13/00 ,  G09G3/04 ,  G01R19/16 ,  G01R13/02

CPC classification number: G01R17/00 ,  G01R13/406

Abstract: A system for displaying the level of a variable electrical signal is disclosed, in which the variable electrical signals are converted into digital form, which are in turn decoded and arranged to consecutively activate a vertical series of indicator elements up and down the series in response to increases and decreases respectively in the digital signal, and with any preceding activated element being deactivated so that only a single individual indicator element corresponding to each digital signal is activated. Accordingly, the rise and fall of the position of the activated indicator element indicates the level of the electrical signal. An arrangement is also disclosed for providing signal limit indication comprising means for comparing the digital signal corresponding to the variable electrical signal with preset digital limit signals which means drives a limit indicator element whenever the generated digital signal is outside the preset values.

Abstract translation: 公开了一种用于显示可变电信号的电平的系统，其中可变电信号被转换成数字形式，其依次被解码和布置成响应于该系列响应于连续地上下串联的一系列指示符元件 分别在数字信号中增加和减少，并且任何先前激活的元件被去激活，使得仅对应于每个数字信号的单独的单个指示元件被激活。 因此，激活的指示元件的位置的上升和下降指示电信号的电平。 还公开了一种用于提供信号限制指示的装置，其包括用于将对应于可变电信号的数字信号与预设的数字限制信号进行比较的装置，这意味着每当产生的数字信号超出预设值时驱动限制指示器元件。

公开(公告)号：US3757298A

公开(公告)日：1973-09-04

申请号：US3757298D

申请日：1972-08-14

Applicant: BENDIX CORP

Inventor： TUMBUSH G

IPC: G06F7/02

CPC classification number: G06F7/026

Abstract: An arrangement for providing an indication when the value of a varying binary digital signal is less than or greater than selectively set lower and upper decimal limits respectively. The arrangement includes a digital counter which is cyclically counted up, the contents of the counter being continuously read in binary form into a pair of one-of-eight converters, the outputs of which are in turn read into a switching matrix. The switching matrix outputs a signal state whenever the converter outputs equal either of a pair of decimal values set on a respective pair of switching matrix sliders corresponding to an upper and lower limit respectively. This signal state is used in conjunction with logic circuitry to gate the ''''less than'''' and ''''greater than'''' outputs of a comparator in which the counter contents and the varying binary digital signal are compared so that the comparator output signal is gated out to an indicator driver circuit whenever the counter contents equal either of the upper or lower limits set by the pair of switching matrix sliders. This gating is controlled by the logic circuitry so that the ''''less than'''' output is gated when the counter contents equals the set lower limit and the ''''greater than'''' output gated when the counter contents equals the set upper limit to provide an output signal whenever the varying binary digital signal either declines below the set lower limit or increases above the upper limit.

公开(公告)号：US3757126A

公开(公告)日：1973-09-04

申请号：US3757126D

申请日：1972-08-28

Applicant: BENDIX CORP

Inventor： TUMBUSH G

IPC: G01B11/00 ,  G01D5/26 ,  G01D5/36 ,  G01D5/38 ,  G01D18/00 ,  G01B11/04

CPC classification number: G01D5/38

Abstract: A method of setting the reading head skew angle and the associated input stage amplifier gain and balance of a Moire fringe transducer system is disclosed which can be carried out with a voltmeter. The procedure involves setting the signal d-c level at zero by means of an amplifier balance potentiometer, measuring the a-c output of the input stage amplifier associated with each channel while adjusting the reading head skew angle to obtain a maximum signal, resetting the d-c level at zero, setting the a-c amplitude at the prescribed level by adjusting the amplifier gain and then measuring and setting the phase angle between square waves produced from the 0* and 90* channel sine waves by measuring the effective a-c value produced by the combined 0* and 90* square waves and adjusting the reading head skew angle to obtain a predetermined a-c reading corresponding to the correct phase angle, and then repeating the procedures involved in the last three steps until all of the conditions are met.