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公开(公告)号：US20250151540A1
公开(公告)日：2025-05-08
申请号：US19013609
申请日：2025-01-08
Inventor： Yongqian LI , Can YUAN , Xuehuan FENG
IPC: H10K59/126 , G09G3/3225 , H10K59/131
Abstract: A display substrate and a display device. The display substrate includes a base substrate, and a plurality of pixel units and a plurality of scanning lines on the base substrate. Each pixel unit includes a plurality of sub-pixels and a light shielding layer, the plurality of sub-pixels is arranged in sequence in a first direction, each sub-pixel includes a sub-pixel driving circuitry and a light-emitting element coupled to each other, and the sub-pixel driving circuitry is configured to provide a driving signal to the light-emitting element. At least a part of the light shielding layer is arranged between the sub-pixel driving circuitry and the base substrate. Each scanning line includes at least a part extending in the first direction, is coupled to a corresponding sub-pixel driving circuitry, and is arranged at a same layer as the light shielding layer.
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公开(公告)号：US20250140182A1
公开(公告)日：2025-05-01
申请号：US18262322
申请日：2022-06-01
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU
IPC: G09G3/3233 , G09G3/32
Abstract: A display panel includes a first pixel driving circuit and a second pixel driving circuit. A data writing transistor and a driving transistor in the first pixel driving circuit, a driving transistor and a data writing transistor in the second pixel driving circuit are sequentially arranged. In the first pixel driving circuit, a first electrode plate of a capacitor is coupled to the driving transistor at a first coupling position and coupled to a first light-emitting device at a second coupling position located at a side of the first coupling position away from the data writing transistor. In the second pixel driving circuit, a first electrode plate of a capacitor is coupled to the driving transistor at a third coupling position and coupled to a second light-emitting device at a fourth coupling position located between the third coupling position and the data writing transistor.
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公开(公告)号：US20250124841A1
公开(公告)日：2025-04-17
申请号：US18291452
申请日：2023-03-31
Inventor： Can YUAN , Yongqian LI , Miao LIU , Dandan ZHOU , Cheng XU
IPC: G09G3/20
Abstract: A driving circuit includes a pull-up node control circuit, a pull-down node control circuit and an output circuit; the pull-up node control circuit controls a potential of the pull-up node under the control of an input signal and a reset signal; the output circuit controls the output terminal to output a signal under the control of the potential of the pull-up node and the potential of the pull-down node; a channel length of at least one transistor among at least some transistors included in the output circuit, at least some transistors whose gate electrodes are electrically connected to the input terminal included in the pull-up node control circuit, and at least some transistors whose gate electrodes are electrically connected to the reset terminal included in the pull-up node control circuit is greater than a channel length of another transistor included in the driving circuit.
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公开(公告)号：US20250113613A1
公开(公告)日：2025-04-03
申请号：US18293316
申请日：2022-08-22
Inventor： Xuehuan FENG , Yongqian LI
Abstract: Provided is an array substrate, including: a gate drive circuit disposed in a non-display region of a base substrate; a plurality of display pads disposed in a bonding region of the base substrate, wherein the plurality of display pads include gate drive signal pads, data signal pads, and voltage signal pads which are arranged in sequence in a first direction; and a plurality of gate connection wirings disposed in the non-display region of the base substrate, wherein a quantity of the gate connection wirings is greater than a quantity of the gate drive signal pads, wherein first ends of the gate connection wirings are electrically connected to the gate drive circuit, with second ends of one part of the gate connection wirings electrically connected to the gate drive signal pads and second ends of another part of the gate connection wirings electrically connected to the voltage signal pads.
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公开(公告)号：US20250098445A1
公开(公告)日：2025-03-20
申请号：US18557562
申请日：2023-01-12
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
IPC: H10K59/131 , G09G3/3233 , H10K59/121 , H10K59/80
Abstract: Pixel circuit, driving control method, display substrate and device are disclosed. The pixel circuit includes a driving circuit, a control circuit and a light-emitting module; the driving circuit generates driving current for driving the light-emitting module under control of control end of the driving circuit; the control circuit is connected to first scanning line, power supply voltage line and second end of the driving circuit, and controls connection between the power supply voltage line and the second end of the driving circuit under control of first scanning signal; second end of the light-emitting module is connected to a cathode voltage line. With the control circuit, branch current can be increased by increasing forward and reverse voltages, such that foreign bodies at dark spots can be burnt out and the dark spots can be changed into normal pixels, thereby improving product yield and displaying quality.
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Patent Agency Ranking
公开(公告)号：US20250089365A1
公开(公告)日：2025-03-13
申请号：US18557810
申请日：2022-07-28
Inventor： Can YUAN , Luke DING , Zhidong YUAN , Liu WU , Yongqian LI , Dacheng ZHANG , Cheng XU , Dandan ZHOU
IPC: H01L27/12 , G09G3/00 , G09G3/3225
Abstract: A display substrate including a base substrate and a driving module arranged on the base substrate, the driving module includes at least one driving unit, and the driving unit includes N stages of driving circuits; N is a positive integer, n is a positive integer less than or equal to N; the nth stage of driving circuit includes a (2n−1)th stage of output circuit, a 2nth stage of output circuit and a first node control circuit; the first node is electrically connected to the (2n−1)th stage of output circuit and the 2nth stage of output circuit respectively through a first connection line; the driving module also includes a scanning line; there are at least two mutually independent overlapping portions between the orthographic projection of the first connection line on the base substrate and the orthographic projection of the scanning line on the base substrate.
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公开(公告)号：US20250056994A1
公开(公告)日：2025-02-13
申请号：US18933239
申请日：2024-10-31
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Meng LI , Dacheng ZHANG , Lang LIU
IPC: H10K59/131
Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.
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公开(公告)号：US20240381716A1
公开(公告)日：2024-11-14
申请号：US18249397
申请日：2022-05-20
Inventor： Luke DING , Yongqian LI , Can YUAN
IPC: H10K59/131
Abstract: The disclosure provides a display substrate, which has a display region and a peripheral region, and includes a base substrate, a plurality of sub-pixels, a first power signal line and a second power signal line at least partially located in the display region, a first power signal bus and a second power signal bus located in the peripheral region; the sub-pixels are located in the display region; the first power signal line and the second power signal line are electrically connected to the first power signal bus and the second power signal bus, respectively; the second power signal bus includes a first part disposed on a side of the first power signal bus close to the display region, and a second part disposed on a side of the first power signal bus away from the display region, so as to at least partially surround the first power signal bus.
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公开(公告)号：US20240371324A1
公开(公告)日：2024-11-07
申请号：US18257521
申请日：2022-04-27
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3233 , H10K59/121 , H10K59/131
Abstract: A display substrate includes a plurality of pixel circuits, and the pixel circuits each include a sensing circuit and a light-emitting control circuit. In a second direction, adjacent three rows of pixel circuits are a first row of pixel circuits, a second row of pixel circuits and a third row of pixel circuits. A region between the first row of pixel circuits and the second row of pixel circuits is a first gap region. In the first row of pixel circuits and the second row of pixel circuits, a sensing circuit of each pixel circuit is closer to the first gap region than a light-emitting control circuit of the pixel circuit, and sensing signal terminals of sensing circuits of two pixel circuits in a same column are a same signal terminal.
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10.发明公开公开(公告)号：US20240355307A1
公开(公告)日：2024-10-24
申请号：US18755710
申请日：2024-06-27
Inventor： Xuehuan FENG , Yongqian LI
CPC classification number: G09G5/006 , G11C19/28 , G09G2310/0286 , G09G2310/08
Abstract: The present disclosure provides a shift register unit, a signal generation unit circuit, a driving method and a display device. The shift register unit includes a first node control circuit, a second node control circuit and an output circuit, the first node control circuit is used to control a potential of a first node; the second node control circuit controls a potential of a second node; the output circuit is used to control and maintain the potential of the first node and the potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the input terminal and the second voltage terminal under the control of the potential of the second node.
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