DISPLAY PANEL AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE
    4.
    发明申请
    DISPLAY PANEL AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE 审中-公开
    显示面板及其驱动方法及显示设备

    公开(公告)号:US20170023738A1

    公开(公告)日:2017-01-26

    申请号:US15135429

    申请日:2016-04-21

    发明人: Yang You Kaixuan Wang

    IPC分类号: G02B6/293

    CPC分类号: G02B6/29389

    摘要: A display panel includes a plurality of input optical paths for transmitting optical waves along a first direction, each of the input optical paths including a light source, a plurality of multimode waveguides and a plurality of circulators, wherein the light source is connected to an input end of the input optical path, and the multimode waveguides and the circulators are provided alternatingly in the input optical path. The display panel further includes a plurality of output optical paths, each output optical path connected to one of the plurality of circulators in one of the input optical paths, respectively, for transmitting optical waves along a second direction, each of the output optical paths including a single-mode waveguide connected to the circulator through an optical filter, the single-mode waveguide configured to output an optical wave filtered by the optical filter.

    摘要翻译: 显示面板包括用于沿着第一方向传输光波的多个输入光路,每个输入光路包括光源,多个多模波导和多个循环器,其中光源连接到输入端 输入光路的端部,并且多路波导和循环器交替地设置在输入光路中。 显示面板还包括多个输出光路,每个输出光路分别连接到一个输入光路中的多个循环器中的一个,用于沿第二方向传输光波,每个输出光路包括 通过光滤波器连接到环行器的单模波导,该单模波导被配置为输出由滤光器滤波的光波。

    Thin-film transistor, array substrate, display panel and display device and fabrication method thereof

    公开(公告)号:US10943926B2

    公开(公告)日:2021-03-09

    申请号:US15556941

    申请日:2017-02-09

    摘要: The present disclosure relates to a thin-film transistor, an array substrate, a display panel and a display device and fabrication methods thereof. The thin-film transistor includes a gate insulation layer, an active layer having a source region, a drain region, and a channel region, a first doping layer on the source region, a second doping layer on the drain region, and at least one third doping layer arranged between the first doping layer and the second doping layer, wherein the first, the second, and the third doping layers have same conductivity type, and wherein the third doping layer is positioned in the channel region and contacts the gate insulation layer, and the third doping layer does not contact the first doping layer and the second doping layer simultaneously, or the third doping layer is positioned on the channel region and only contacts the first or the second doping layer.