MANUFACTURING METHOD OF DISPLAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

    公开(公告)号:US20200312881A1

    公开(公告)日:2020-10-01

    申请号:US15777118

    申请日:2017-09-26

    IPC分类号: H01L27/12

    摘要: A manufacturing method of a display substrate, an array substrate and a display device are provided. The method includes forming a first wire, a first insulation layer, a first and second metal layer, and a photoresist layer; forming a photoresist retained pattern above the first wire; forming a second and first metal layer retained pattern under the photoresist retained pattern; forming a second insulation layer with a thickness less than or equal to a sum of thicknesses of the first and second metal layer; the second insulation layer forming a fracture region at a boundary between a part covering the first insulation layer and another part covering the second metal layer retained pattern; removing the first and second metal layer retained patterns by a wet etch process to expose the first insulation layer; and forming a contact hole exposing the first wire.

    Pixel Array and Fabrication Method Thereof
    6.
    发明申请

    公开(公告)号:US20200013806A1

    公开(公告)日:2020-01-09

    申请号:US16405126

    申请日:2019-05-07

    IPC分类号: H01L27/12 G09G3/20 G09G3/22

    摘要: The present disclosure provides a pixel array and a fabrication method thereof. The pixel array includes a plurality of gate lines and a plurality of data lines which are arranged intersected and insulated and a pixel unit disposed at a position where each of the plurality of gate lines and each of the plurality of data lines are intersected. The pixel unit includes a thin film transistor (TFT).The width-to-length ratios of channels of the TFTs are sequentially increased in such a manner that the width-to-length ratios of the channels of the TFTs in the pixel units positioned in a same row (and/or a same column) are sequentially increased along a scanning direction of the gate line coupled to gate electrodes of the TFTs in the same row (and/or along a data writing direction of the data line coupled to the source electrodes of the TFTs in the same column).

    DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE

    公开(公告)号:US20210313356A1

    公开(公告)日:2021-10-07

    申请号:US16761231

    申请日:2019-10-28

    IPC分类号: H01L27/12 G03F7/00 G03F7/16

    摘要: The present disclosure provides a display substrate, a method for preparing the same, and a display device including the display substrate. The method includes: forming a conductive layer; forming a first photoresist pattern and a second photoresist pattern on the conductive layer, in which the adhesion between the first photoresist pattern and the conductive layer is less than the adhesion between the second photoresist pattern and the conductive layer; and etching the conductive layer by using the first photoresist pattern and the second photoresist pattern as masks to form a first conductive pattern and a second conductive pattern, respectively, in which a line width difference between the first conductive pattern and the first photoresist pattern is greater than a line width difference between the second conductive pattern and the second photoresist pattern.

    ARRAY SUBSTRATE, PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE

    公开(公告)号:US20210296406A1

    公开(公告)日:2021-09-23

    申请号:US17264283

    申请日:2020-05-12

    IPC分类号: H01L27/32 H01L51/56 H01L51/52

    摘要: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.