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公开(公告)号:US10412826B2
公开(公告)日:2019-09-10
申请号:US15944206
申请日:2018-04-03
发明人: Pucha Zhao , Guoqing Zhang , Xiaopeng Bai , Hongwei Gao , Weifeng Wang , Yanbin Dang , Haotian Chen
IPC分类号: H01H85/046 , H05K3/30 , H05K1/02
摘要: The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I
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公开(公告)号:US11232727B2
公开(公告)日:2022-01-25
申请号:US16466328
申请日:2018-10-31
发明人: Pucha Zhao , Guoqing Zhang , Xiaopeng Bai , Weifeng Wang , Yanbin Dang , Zhixin Guo , Xingliang Wang , Haotian Chen
摘要: A substrate, a panel, a detection device and an alignment detection method are provided. The substrate includes first signal connection pins arranged in parallel side by side and at least one first alignment detection pin, wherein the at least one first alignment detection pin is located on at least one side of the first signal connection pins in an arrangement direction of the first signal connection pins, and arranged in parallel with the first signal connection pins.
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公开(公告)号:US10510278B2
公开(公告)日:2019-12-17
申请号:US16213210
申请日:2018-12-07
发明人: Weifeng Wang , Guoqing Zhang , Hongxia Yang , Yu Fu , Xingliang Wang , Zhixin Guo , Yanbin Dang , Xiaowei Wang , Jie Wu , Feiwen Tian , Pucha Zhao , Chenwei Wang , Xuepeng Ji
摘要: The present disclosure provides a signal loading method and a signal generator. The signal loading method includes: loading a first pair of voltage signals to at least one pair of separate signal channels for a time period, respectively, wherein the first pair of voltage signals have a first voltage difference therebetween; and determining whether a short circuit occurs in the at least one pair of signal channels within the time period, and if it is determined that no short circuit occurs in the at least one pair of signal channels within the time period, loading a second pair of voltage signals having a second voltage difference therebetween to the at least one pair of signal channels at the end of the time period. The second voltage difference is greater than the first voltage difference.
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