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    Gate drive circuit and display panel
    4.
    发明授权
    Gate drive circuit and display panel 有权

    公开(公告)号：US11170696B2

    公开(公告)日：2021-11-09

    申请号：US16321485

    申请日：2018-05-11

    申请人： BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

    发明人： Yan Li ,  Meiling Jin ,  Xiaobo Xie ,  Lingyun Shi ,  Wei Sun

    IPC分类号： G09G3/20 ,  G11C19/28

    摘要： A gate drive circuit and a display panel are provided. The gate drive circuit controls, by adding a control module, the potential at a key node of an output module in a touch-control phase, that is, outputting a low-level signal of a signal switching end to a first node of the output module of the current-stage shift register in the touch-control phase, so as to stabilise the potential of the key node, i.e. the first node in the touch-control phase, thereby avoiding the case where the potential at the key node is in a floating state and thus is capacitively coupled and deviates from a stable potential; and a transition to a display stage before the touch-control state ends is made, and a high-level signal of the signal switching end is output to the first node, so as to pull up the potential at the first node.

    Gate driving unit, driving method thereof, gate driving circuit and display device
    5.
    发明授权
    Gate driving unit, driving method thereof, gate driving circuit and display device 有权

    公开(公告)号：US11114004B2

    公开(公告)日：2021-09-07

    申请号：US16094615

    申请日：2018-03-14

    申请人： BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

    发明人： Yan Li ,  Lingyun Shi ,  Wei Sun ,  Xiaobo Xie ,  Meiling Jin

    IPC分类号： G09G3/20

    摘要： The present disclosure provides a gate driving unit, a driving method thereof, a gate driving circuit and a display device. The gate driving unit includes an input resetting module, a storage module, a pull-up node control module, a pull-down node control module and an output module. The gate driving unit further includes a clock signal control module, connected to a first control signal end, a second control signal end, a first reference clock signal end, a second reference clock signal end, a first clock signal end and a second clock signal end, and configured to, under the control of a first control signal from the first control signal end and a second control signal from the second control signal end, output clock signals at a same frequency and in opposite phases to the first clock signal end and the second clock signal end respectively in accordance with a first reference clock signal from the first reference clock signal end and a second reference clock signal from the second reference clock signal.