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公开(公告)号：US11456045B2
公开(公告)日：2022-09-27
申请号：US15934833
申请日：2018-03-23
发明人： Jian Tao , Li Sun , Wei Xue , Hongmin Li
摘要： The embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit and a display apparatus. The shift register comprises an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal; an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal.
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公开(公告)号：US11423823B2
公开(公告)日：2022-08-23
申请号：US17255665
申请日：2020-06-02
发明人： Wei Xue , Hongmin Li , Yue Shi , Qinghua Jiang
摘要： The present disclosure provides a shift register including: a pre-charge reset circuit and an output circuit, the pre-charge reset circuit is configured to write, in a pre-charge stage, an input signal in an active level state into the pull-up node in response to the control of a first control signal, and write, in a reset stage, an input signal in an inactive level state into the pull-up node in response to the control of a second control signal; the output circuit is configured to write, in an output stage, a clock signal in an active level state into a signal output terminal in response to the control of an electric signal in an active level state at the pull-up node, and write, in the reset stage, a clock signal in an inactive level state into the signal output terminal in response to the control of the second control signal.
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公开(公告)号：US11237662B2
公开(公告)日：2022-02-01
申请号：US16328366
申请日：2018-06-08
发明人： Liqing Liao , Hongmin Li , Zhifu Dong
摘要： Embodiments of the present disclosure provide a touch display substrate, a method for manufacturing the same, a driving method thereof, and a display device thereof. The touch display substrate includes a substrate, a plurality of electrode blocks, independent of each other and arranged in an array, disposed on the substrate, and a switching device disposed between the adjacent electrode blocks. The electrode block is configured to receive a common voltage during a display period and receive a touch scan signal during a touch period. The switching device is configured to electrically connect the adjacent electrode blocks during the display period and electrically isolate the adjacent electrode blocks from each other during the touch period.
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公开(公告)号：US20210216170A1
公开(公告)日：2021-07-15
申请号：US16081513
申请日：2018-04-09
发明人： Ying Wang , Hongmin Li , Dong Wang , Zhifu Dong , Jian Tao , Li Sun
摘要： The present disclosure is related to a substrate. The substrate may include a plurality of electrode patterns. Each of the plurality of the electrode patterns may include a first electrode and a plurality of second electrodes connected to the first electrode. A shape of second electrodes of an electrode pattern may be complementary to a shape of second electrodes of at least one electrode pattern adjacent to the electrode pattern.
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公开(公告)号：US10923020B2
公开(公告)日：2021-02-16
申请号：US16134764
申请日：2018-09-18
发明人： Wei Xue , Hongmin Li , Ying Wang , Fengjing Tang , Li Sun
IPC分类号： G11C19/00 , G09G3/20 , G11C19/28 , G09G3/3266 , G09G3/36
摘要： The present disclosure provides a shift register unit. The shift register unit includes an input module, an output module and an output control module. The input module is connected to an input signal terminal, a first power supply signal terminal and a pull-up node, and is configured to transmit a first power supply signal to the pull-up node. The output module is connected to the pull-up node, a clock signal terminal and an output control node, and is configured to transmit a clock signal to the output control node. The output control module is connected to the output control node, the clock signal terminal and a signal output terminal, and is configured to transmit a signal of the output control node to the signal output terminal under the control of the clock signal.
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公开(公告)号：US10770002B2
公开(公告)日：2020-09-08
申请号：US16134472
申请日：2018-09-18
发明人： Wei Xue , Hongmin Li , Zhifu Dong , Fengjing Tang
IPC分类号： G11C19/00 , G09G3/3266 , G09G3/36 , G11C19/28
摘要： A shift register circuit includes an input terminal, a reset terminal, a first scan voltage terminal, a second scan voltage terminal, a first reference voltage terminal, a second reference voltage terminal, a clock terminal, an output terminal, an input circuit, a first control circuit, a second control circuit, and an output circuit. The first control circuit is configured to supply a second reference voltage applied at the second reference voltage terminal to a first node and bring the second reference voltage terminal into conduction with the output terminal in response to a second node being at an active potential. The second control circuit is configured to supply a first reference voltage applied at the first reference voltage terminal to the first node and bring the first reference voltage terminal into conduction with the output terminal in response to a third node being at an active potential.
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公开(公告)号：US10658061B2
公开(公告)日：2020-05-19
申请号：US16332193
申请日：2018-08-21
发明人： Liqing Liao , Hongmin Li , Zhifu Dong , Silin Feng
摘要： A shift register circuit, a driving method, a gate driving circuit, and a display device are provided. The shift register circuit includes a clock signal adjustment circuit and a self-control conduction circuit; the clock signal adjustment circuit includes a first clock signal input terminal, a second clock signal input terminal, and a clock signal adjustment output terminal; the clock signal adjusting circuit is configured to, in the case that the first clock signal and the second clock signal are both at a second level, output a first level via a clock signal adjustment output terminal; the self-control conduction circuit is configured to, in the case that the pull-up node is at the first level, control the clock signal adjustment output terminal connect with a pull-up node, or in the case that the pull-up node is at a second level, disconnect the clock signal adjustment output terminal from the pull-up node.
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公开(公告)号：US20190206504A1
公开(公告)日：2019-07-04
申请号：US16168898
申请日：2018-10-24
发明人： Jian Tao , Zhifu Dong , Hongmin Li
摘要： A shift register, a driving method, a gate driving circuit and a display device are provided. The shift register includes: a reset circuit, a latch circuit, an output control circuit, and an output circuit which are series connected in sequence. The reset circuit is configured to provide an input signal from the input signal end for the pull-up node under the control of a reset signal from the reset signal end; the latch circuit is respectively connected to the input signal end and the pull-up node, and is configured to control the potential of the pull-up node; the output control circuit is respectively connected to the pull-up node, a dock signal end, and a control node, and is configured to control the potential of the control node; and the output circuit is respectively connected to the control node and an output end, and is configured to control the potential of the output end. The shift register reduces the layout area occupied by the gate driving circuit and can effectively save power consumption and improve the anti-interference ability of the signal.
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公开(公告)号：US10311814B2
公开(公告)日：2019-06-04
申请号：US15504015
申请日：2016-09-09
发明人： Zhifu Dong , Hongmin Li , Ping Song , Liqing Liao
IPC分类号： G02F1/135 , G09G3/36 , G02F1/1345 , G02F1/1362 , G06F3/041 , H01L27/12 , G02F1/1333
摘要： The disclosure provides an array substrate, a display panel, a display device and a display method. The array substrate comprises a display region provided with a plurality of data lines therein and a wiring region around the display region and provided with a plurality of leading wires therein. The plurality of leading wires are connected with the plurality of data lines respectively in a one-to-one correspondence way. The plurality of leading wires comprise a plurality of first leading wires and a plurality of second leading wires insulatively arranged in different layers. The plurality of first leading wires and the plurality of second leading wires comprise at least one pair of overlapped first and second leading wires to which data signals having the same polarity are input.
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公开(公告)号：US10170069B2
公开(公告)日：2019-01-01
申请号：US15680441
申请日：2017-08-18
发明人： Wei Xue , Hongmin Li , Ping Song , Zhifu Dong
摘要： A shift register includes an input circuit, a first reset circuit, an output circuit, a second reset circuit and a first pull-down control circuit. The input circuit may control a voltage of the first node according to a reset signal from a reset signal terminal. The first reset circuit may reset the voltage of the first node according to the reset signal from the reset signal terminal. The output circuit may control an output signal of a signal output terminal according to the voltage of the first node. The second reset circuit may reset the voltage of the first node and the output signal according to a voltage of a second node. The first pull-down control circuit may control the voltage of the second node according to the voltage of the first node based on a first auxiliary voltage signal and a second auxiliary voltage signal, wherein a phase of the first auxiliary voltage signal is opposite to a phase of the second auxiliary voltage signal, and each duty cycles is 50%.
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