公开(公告)号：US20160365967A1

公开(公告)日：2016-12-15

申请号：US14795840

申请日：2015-07-09

Applicant: BROADCOM CORPORATION

Inventor： Chung Ming TU ,  Peiqing WANG ,  Ahmad CHINI ,  Yencheng CHEN ,  Mehmet Vakif TAZEBAY ,  Bazhong SHEN

IPC: H04L7/00

CPC classification number: H04L7/10 ,  H04L7/048 ,  H04L12/413

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

Abstract translation: 实现单对以太网链路建立的主题系统的主要装置可以包括至少一个处理器电路。 至少一个处理器电路可以被配置为将第一同步序列发送到辅助设备，并且随后检测由辅助设备发送的与第一同步序列不同的第二同步序列。 同步序列可以是具有强自相关特性的伪噪声序列。 至少一个处理器电路可以被配置为在完成第二同步序列的检测之后等待预定量的时间，然后可以启动训练阶段。 训练阶段可以包括交换由主设备和次设备使用的加法器扰频器的扰频器状态。 所述至少一个处理器电路可以被配置为在完成训练时进入数据模式。 在数据模式下，数据进行前向纠错编码，然后加扰。