Abstract:
A data processing method and a system for performing the data processing method, in which data are transferred between various network subscribers of a network in a communication cycle and multiple data processing devices are provided as network subscribers. A respective process cycle is run through by each of the multiple data processing devices. The communication cycle is synchronized here with the process cycle of at least one of the multiple data processing devices such that, during a temporal run-through of the communication cycle, a predetermined process step of the process cycle of at least one of the multiple data processing devices is carried out during a time interval, assigned to this predetermined process step, of the communication cycle.
Abstract:
Systems, methods, apparatuses, and computer program products for facilitating robustness for synchronization signal block (SSB) are provided. A network node may attempt to transmit SSBs in first positions. For example, the network node may perform a listen-before-talk (LBT) procedure prior to transmitting the SSBs, and transmissions of the SSBs may fail or succeed based on failure or success of the LBT procedure. If the transmissions fail, the network node may attempt to transmit the failed SSBs in second SSB positions. For example, the second SSB positions may be associated with the first positions, and may be reserved for retransmission of SSBs that fail in the corresponding first positions. If the network node transmits the SSBs, the UE may perform various operations described herein including, e.g., determining whether the SSBs were transmitted in the first positions or the second positions and/or an SSB index or timing.
Abstract:
The present invention relates to a method for estimating a bit error probability using an error rate ratio of a frame synchronization word, to lower computational complexity such that the method can be implemented in a relatively simple and economical way at a high computational speed. The method includes the steps of: a) defining error rate ratios of frame synchronization words; b) setting a weighted least squares cost function with weights greater than or equal to 0 for the bit error probability using the error rate ratios of the frame synchronization words set in the step a); c) obtaining an estimated bit error probability value that minimizes the cost function set in the step b); and d) sequentially obtaining the weights so that a mean squared error of the estimated bit error probability value obtained in the step c) becomes small.
Abstract:
Systems and methods are provided for enabling reliable signaling in the presence of strong phase noise and frequency offset. To this end, a method is provided comprising receiving, at a receiver, a communication signal, including data, from a transmitter via a communication channel, and jointly tracking and jointly correcting phase noise errors and frequency errors in the communication signal with a joint detector using an iterative feedback correction process between an output decoder of the receiver and the joint detector.
Abstract:
In one implementation, a receiver has a module to calculate the cross-correlation between a portion of a digital representation of a received signal and a reference signal. The receiver also has a module to generate an estimate of a portion of a message potentially included in the digital representation of the received signal and a screening module to determine the likelihood that the received signal includes a message. For a received signal that is determined likely to include a message, the receiver includes a carrier refinement module to shift the frequency of carrier pulses in the digital representation of the received signal toward a desired frequency and to align the phase of carrier pulses in the digital representation of the received signal with a desired phase and a coherent matched filter to recover the message from the digital representation of the received signal.
Abstract:
Methods, systems, and devices for wireless communication are described. A base station may identify a transport block for transmission that includes an information component and an error detection code. The base station may transmit a first encoded message during a first transmission time. The first encoded message may be obtained by encoding the transport block cyclically shifted a first bit length. The base station may transmit a second encoded message during a second transmission time. The second encoded message may be obtained by encoding the transport block cyclically shifted a second bit length. The relative time distance between the first and second transmission times may convey an indication of the difference between the first bit length and the second bit length.
Abstract:
Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.
Abstract:
A wireless receiver is disclosed. The wireless receiver includes a phased array antenna panel having a plurality of antennas, and a low resolution analog-to-digital (A/D) converter coupled to each of the plurality of antennas, where the low resolution A/D converter is configured to provide a digital output based on comparing a reference value with a sum of noise value and signal value of an analog input received by the corresponding one of the plurality of antennas. Noise signals received by the plurality of antennas are uncorrelated, and a signal to noise ratio (SNR) of the analog input can be less than one. The low resolution A/D converter can be a one-bit A/D converter. The one-bit A/D converter can be a comparator receiving the sum of noise value and signal value as one comparator input, and receiving the reference value as another comparator input.
Abstract:
A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.
Abstract:
This communication system ensures the security of a communication message with a low computational load. Communication units are capable of exchanging a communication message containing a check bit. The check bit is used to determine the reliability of the communication message. Communication unit, which transmits the communication message, is equipped with a storage position determination part. The storage position determination part determines one of multiple positions within the communication message where the check bit can be stored as a storage position. The communication unit generates a communication message with the check bit stored at the storage position and transmits the communication message. Communication unit, which receives the communication message, is equipped with a storage position determination part. The storage position determination part determines the storage position of the check bit in the communication message in accordance with the manner the storage position was determined.