公开(公告)号：US09577787B2

公开(公告)日：2017-02-21

申请号：US14627539

申请日：2015-02-20

Applicant: Broadcom Corporation

Inventor： Chung Ming Tu ,  James Graba ,  Peiqing Wang ,  Ahmad Chini ,  Yencheng Chen ,  Ba-Zhong Shen ,  Mehmet Vakif Tazebay

IPC: G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  H04L12/12

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04L1/0045 ,  H04L1/0057 ,  H04L12/12 ,  Y02D50/42

Abstract: A communication technique for energy efficient Ethernet (EEE) employs a systematic block forward error correcting code (FEC). The technique aligns a low power idle (LPI) refresh signal with the FEC frame. The refresh signal includes a known reference sequence, FEC systematic symbols, and FEC parity symbols. The technique may apply shortened FEC encoding and decoding on the partial data symbols and the parity symbols.

Abstract translation: 能效以太网（EEE）的通信技术采用系统块前向纠错码（FEC）。 该技术将低功耗空闲（LPI）刷新信号与FEC帧对齐。 刷新信号包括已知的参考序列，FEC系统符号和FEC奇偶校验符号。 该技术可以对部分数据符号和奇偶校验符号应用缩短的FEC编码和解码。

公开(公告)号：US10027471B2

公开(公告)日：2018-07-17

申请号：US14795840

申请日：2015-07-09

Applicant: BROADCOM CORPORATION

Inventor： Chung Ming Tu ,  Peiqing Wang ,  Ahmad Chini ,  Yencheng Chen ,  Mehmet Vakif Tazebay ,  Bazhong Shen

IPC: H04L7/10 ,  H04L12/413 ,  H04L7/04

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

公开(公告)号：US20160204900A1

公开(公告)日：2016-07-14

申请号：US14627539

申请日：2015-02-20

Applicant: Broadcom Corporation

Inventor： Chung Ming Tu ,  James Graba ,  Peiqing Wang ,  Ahmad Chini ,  Yencheng Chen ,  Ba-Zhong Shen ,  Mehmet Vakif Tazebay

IPC: H04L1/00 ,  G06F11/10

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04L1/0045 ,  H04L1/0057 ,  H04L12/12 ,  Y02D50/42

Abstract: A communication technique for energy efficient Ethernet (EEE) employs a systematic block forward error correcting code (FEC). The technique aligns a low power idle (LPI) refresh signal with the FEC frame. The refresh signal includes a known reference sequence, FEC systematic symbols, and FEC parity symbols. The technique may apply shortened FEC encoding and decoding on the partial data symbols and the parity symbols.

Abstract translation: 能效以太网（EEE）的通信技术采用系统块前向纠错码（FEC）。 该技术将低功耗空闲（LPI）刷新信号与FEC帧对齐。 刷新信号包括已知的参考序列，FEC系统符号和FEC奇偶校验符号。 该技术可以对部分数据符号和奇偶校验符号应用缩短的FEC编码和解码。