公开(公告)号：US3878513A

公开(公告)日：1975-04-15

申请号：US22443572

申请日：1972-02-08

Applicant: BURROUGHS CORP

Inventor： WERNER JOHN R

IPC: G06F9/40 ,  G06F12/08 ,  G06F7/00 ,  G06F13/00

CPC classification number: G06F9/4425 ,  G06F12/08 ,  G06F2212/251 ,  G06F2212/253

Abstract: While executing program code arranged in nested blocks, a data processing system accumulates words in a stack storage means comprising a pair of registers coupled to an arithmetic unit and supplying thereto operands for processing; a plurality of memory locations in a relatively large-capacity, low-speed memory; and a relatively small-capacity, high-speed memory having a plurality of addressable extension locations. Register means are set to associate the extension locations in one-to-one correspondence with a group of memory locations so as to define corresponding pairs of locations. Each pair is reserved for storing a different stack word and has four occupancy conditions. Before the actual accumulation of the stack word for which the pair is reserved, the pair is in a first condition wherein both locations of the pair are unoccupied. After actual accumulation, the pair is either in a second condition wherein only the extension is occupied, or in a third condition wherein only the memory location is occupied, or in a fourth condition wherein both locations are occupied. Preferably each extension location has occupied and copy indicating storage cells having four states each indicating one of the four possible conditions. Stack words forming the record of execution of a first program block are initially accumulated in the extension locations. When a second program block nested within the first program block is entered the record of execution of the first block is transferred to the presently corresponding memory locations and then the associating register means is set to associate the extension registers with a different group of memory locations so that the extension locations are available to store stack words for the second block. The stack includes a linked list of control words containing stack depth information indicating the number of stack words accumulated in executing each block. Upon a transfer of control from the second block back to the first block the stack depth information is used to set the associating register means so that the required number of extension locations are again reserved for storing the previously accumulated record of execution of the first block. Instead of indiscriminately transferring the record of execution of the first block back to such reserved extension locations, the occupancy and copy indicating storage cells for each such reserved extension location are set to indicate that only the respective memory location is occupied. Thus upon a further transfer of control to another block, the occupancy and copy indicating storage cells provide information used to eliminate unnecessary transfers of words to memory locations already storing the proper words.

公开(公告)号：US3665404A

公开(公告)日：1972-05-23

申请号：US3665404D

申请日：1970-04-09

Applicant: BURROUGHS CORP

Inventor： WERNER JOHN R

IPC: G06F13/14 ,  G06F9/46 ,  G06F13/26 ,  G06F15/16 ,  G06F15/177 ,  G06F9/18

CPC classification number: G06F13/26

Abstract: A data processing system has a plurality of processors each including an interrupt handler for interrupting the execution of object programs and controlling the handling of interrupt conditions. Apparatus distributes the load of handling a class of external interrupts between the processors on a dynamic priority basis. For example, if the processor having highest priority for handling the interrupt related to a particular input/output unit is busy handling an uninterruptable procedure or is otherwise unavailable when the input/output unit requires attention, the apparatus couples an interrupt transfer signal to the processor having the next highest priority and thereby enables the interrupt handler within that processor to service the input/output unit. Each processor within the system can include circuitry for generating transfer signals to enable any one of the processors to service each input/output unit.

公开(公告)号：US3629854A

公开(公告)日：1971-12-21

申请号：US3629854D

申请日：1969-07-22

Applicant: BURROUGHS CORP

Inventor： HAUCK ERWIN A ,  WERNER JOHN R

IPC: G06F13/10 ,  G06F9/46 ,  G06F13/37 ,  G06F15/16 ,  G06F15/177

CPC classification number: G06F13/37

Abstract: A computer having any number of processors of equal capability in the system, each processor being able to scan all peripheral devices over a common bus, with priority resolution being provided by connecting the processors in a closed loop on which is circulated a priority bit. Only the processor receiving the bit can utilize the common bus and circulation of the bit is interrupted by the processor utilizing the common bus.