公开(公告)号：US3693161A

公开(公告)日：1972-09-19

申请号：US3693161D

申请日：1970-07-09

Applicant: BURROUGHS CORP

Inventor： PRICE WILLIAM CHANDLER ,  HAUCK ERWIN A ,  VIGIL JACOB F

IPC: G06F13/40 ,  G06F15/177 ,  H04J3/12 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F15/177

Abstract: There is described a computer system in which one or more processors can interrogate, on command, the input/output system to determine whether communication paths are available to the respective peripheral units. The input/output system has one or more multiplexors which service a number of input/output channels, each channel having a peripheral control unit that controls one or more peripheral devices. Some peripheral devices are operated by more than one peripheral control unit and associated channel through a switching exchange. The input/output system, in response to an interrogation command executed by any of the processors and identifying a selected peripheral device, returns information to the processor indicating whether or not a communication path is available to the designated peripheral device and, if more than one channel is available, which multiplexor has a channel available to that device. The processor then can initiate an input/output operation between the particular unit and memory.

Abstract translation: 描述了一种计算机系统，其中一个或多个处理器可以根据命令询问输入/输出系统以确定通信路径是否可用于各个外围单元。 输入/输出系统具有服务于多个输入/输出通道的一个或多个多路复用器，每个通道具有控制一个或多个外围设备的外围控制单元。 一些外围设备由多个外围控制单元和相关通道通过切换交换来操作。 输入/输出系统响应于任何处理器执行的询问命令并识别选定的外围设备，向处理器返回指示通信路径是否可用于指定的外围设备的信息，如果多于一个 通道可用，哪个多路复用器具有可用于该设备的通道。 然后，处理器可以启动特定单元和存储器之间的输入/输出操作。

公开(公告)号：US3548384A

公开(公告)日：1970-12-15

申请号：US3548384D

申请日：1967-10-02

Applicant: BURROUGHS CORP

Inventor： BARTON ROBERT S ,  CREECH BOBBY A ,  DENT BENJAMIN A ,  HAUCK ERWIN A ,  MCKEEMAN WILLIAM M

IPC: G06F9/45 ,  G06F9/40 ,  G06F9/44 ,  G06F12/00 ,  G06F7/00

CPC classification number: G06F9/4425

Abstract: 1,242,989. Data processing. BURROUGHS CORP. 30 Sept., 1968 [2 Oct., 1967], No. 4513/71. Divided out of 1,233,925. Heading G4A. In data processing apparatus, mark words in stack storage areas link such areas together by each containing a value which references another mark word, a mark word not containing the value being stored in a stack area currently in use, a reference word in the stack area currently in use having a value referencing a mark word for the stack area containing a programme word which refers to a new procedure, there being means for combining this value with the mark word for the stack area currently in use to provide a link therein to the stack area containing the programme word. The disclosure is as in the parent.

公开(公告)号：US3546677A

公开(公告)日：1970-12-08

申请号：US3546677D

申请日：1967-10-02

Applicant: BURROUGHS CORP

Inventor： BARTON ROBERT S ,  CREECH BOBBY A ,  DENT BENJAMIN A ,  HAUCK ERWIN A ,  MCKEEMAN WILLIAM M

IPC: G06F9/40 ,  G06F9/46 ,  G06F12/10 ,  G06F9/20

CPC classification number: G06F9/4425 ,  G06F9/463 ,  G06F12/10

Abstract: 1,233,926. Data processing. BURROUGHS CORP. 30 Sept., 1968 [2 Oct., 1967], No. 46291/68. Heading G4A. A data processing system has a memory containing a plurality of first-in, last-out stacks of information and can access a desired word using a stack base address and an increment. A core memory can store a control table, a data descriptor array, a segment dictionary, and last-in-first-out job stacks. Transistor flip-flop display registers D0, D1, D2, D3 ... point to (contain the absolute address of) MSCW mark words in some of these stored entities as shown in Figs. 2, 4. Referring to Fig. 2, assuming job no. 3 is being processed, registers S, BOSR point to the top and bottom respectively of job stack no. 3. If a "load value" operator is read from memory for execution, the IRWS word at the top of job stack no. 3 is retrieved. If a (job) stack number in it specifies the same stack, i.e. in this case is equal to 3, DISP and 8 fields from the IRWS are added to the contents of BOSR to address memory to obtain a parameter which is loaded on to the top of the current job stack viz. stack no. 3. If the stack number in the IRWS specified a different stack, the contents of display register D0 (pointing to the base of the control table) are incremented by 2 to retrieve a DD from the control table which contains an ADDRESS field pointing to the base of the data descriptor array. The stack number specified in the IRWS is added to the ADDRESS field to retrieve a DD from the data descriptor array, an ADDRESS field of which points to the base of the required stack. This ADDRESS field is added to the DISP and 8 fields from the IRWS to retrieve the parameter which is loaded on to the top of the current job stack, viz. stack no. 3. An IRW word could have been used instead of an IRWS word in which case it would select a display register and provide a field #, the latter being added to the contents of the display register to address memory and obtain the parameter which is loaded on to the stack as before. Referring to Fig. 4 and assuming job no. 2 is being processed and an "enter" operator is read from memory, the IRW shown in job stack no. 2 is retrieved. The IRW selects a display register and provides a 8 field which is added to the display register contents to address memory to retrieve the PCW shown in job stack no. 2 (this PCW relating to procedure C which is to be "entered"). Fields of the PCW are inserted into registers in the computer for use during execution of procedure C. The PCW also selects the display register D1 (which points to the base of the segment dictionary) and provides an increment value which is added to its contents to retrieve an SD from the segment dictionary. An ADDRESS field in this SD points to (the starting address of) the required procedure C which can now be executed. An IRWS might have been used instead of the IRW in which case DISP and # fields in it are added to the contents of the BOSR to retrieve the PCW which is then used as before. The SD also specifies the length of the procedure. The entities pointed to by SD and DD words may be in peripheral disc storage rather than the core memory, this being indicated by a field in the SD or DD. If so, the entity is moved into core memory when required. The PCW also specifies the address of the first operator, and the machine state required. Thus procedures can be shared between jobs. Separate computers may work in parallel on the jobs. Parts of job stacks may be shared between jobs. The hardware facilitates handling of ALGOL or PL/I programmes.

公开(公告)号：US3439354A

公开(公告)日：1969-04-15

申请号：US3439354D

申请日：1965-05-24

Applicant: BURROUGHS CORP

Inventor： BEHR MICHAEL I ,  HAUCK ERWIN A

IPC: G01P1/10 ,  G11B15/52 ,  G11B5/00

CPC classification number: G11B15/52 ,  G01P1/106

公开(公告)号：US3611312A

公开(公告)日：1971-10-05

申请号：US3611312D

申请日：1969-08-21

Applicant: BURROUGHS CORP

Inventor： BARTON ROBERT S ,  CREECH BOBBY A ,  DENT BENJAMIN A ,  HAUCK ERWIN A ,  MCKEEMAN WILLIAM M

IPC: G06F9/46 ,  G06F9/48 ,  H04L11/00

CPC classification number: G06F9/4812

Abstract: A data-processing system has a memory and a controllable operator control network operating in either of two different states for execution of operators and processing interrupts. A state control device is coupled to the controllable operator control network and has first and second states for causing the controllable operator control network to assume first and second states respectively. A first register stores operators for controlling the sequence of operation of the operator control network. A second register stores procedure reference words which have a coded signal therein indicative of either of two required states of the operator control network. The state control device is set to one state or the other depending on the coded signal in the stored reference word thereby establishing the state of the operator control network. A method for setting the state control device is also disclosed.

公开(公告)号：US3408632A

公开(公告)日：1968-10-29

申请号：US55502566

申请日：1966-06-03

Applicant: BURROUGHS CORP

Inventor： HAUCK ERWIN A

IPC: G06F13/22 ,  G11C15/04

CPC classification number: G11C15/04 ,  G06F13/22

公开(公告)号：US3886522A

公开(公告)日：1975-05-27

申请号：US44701574

申请日：1974-02-28

Applicant: BURROUGHS CORP

Inventor： BARTON ROBERT S ,  HAUCK ERWIN A ,  LYLE DON M

IPC: G06F9/40 ,  G06F9/44 ,  G06F11/00 ,  G06F15/16 ,  H04L1/00

CPC classification number: G06F11/076 ,  G06F9/4425 ,  G06F9/4436 ,  G06F15/16 ,  H04L1/004

Abstract: A character-serial electronic digital computer utilizing a four character vocabulary, each character being represented by two binary bits, is structured to process character-serial data arriving at the computer in a manner specified and initiated by the arriving data. Data structures that may represent program or operations to be performed on data arriving at the computer input are stored in the computer''s storage area in the form of nested data structures that may be illustrated as tree structures in which each node of the tree structure represents an operation. Data structures that may represent operands are supplied to the computer also in a nested organization. This operand data addresses a certain node or operation resident in the computer storage area. The linking up of the arriving operand data with its program data triggers execution of the operation. In a case where more than one operand is needed before an operation can be performed, the arrival of a first operand without the second causes storage of the first operand until arrival of the second operand. Arrival of the second operand triggers the operation to begin. This interrelationship of program data and operand data, that is, the dynamic data being linked with the static data to trigger the operation, exists whether the program data is stored and static or the operand data is stored and static. Utilizing a four character vocabulary, to represent data, two of the characters being utilized to indicate the beginning and end of a data field, facilitates the implementation of an error checking technique wherein only sensed characters indicating the beginning and end of a data field are counted. The utilization of beginning and end of data field characters in the data structures consisting of nested data fields permits at will expansion and contraction of the fields within it.

公开(公告)号：US3555513A

公开(公告)日：1971-01-12

申请号：US3555513D

申请日：1967-10-11

Applicant: BURROUGHS CORP

Inventor： HAUCK ERWIN A ,  VIGIL JACOB F

IPC: G06F9/46 ,  G06F12/00 ,  G06F12/02 ,  G06F15/16 ,  G06F15/177 ,  G06F15/40

CPC classification number: G06F12/0284

Abstract: AN ADDRESSABLE MEMORY UNIT IS SHARED BY TWO PROCESSORS, EACH INCLUDING A SOURCE OF MEMORY ADDRESSES. THE MEMORY ADDRESS VALUES IN THE FIRST AND SECOND PROCESSORS ARE AT LEAST IN PART THE SAME. IN THE COURSE OF THE OPERATION OF THE PROCESSORS, THE ADDRESS VALUES ARE COUPLED TO THE MEMORY UNIT. THE ADDRESS VALUES ARE COUPLED TO PROCESSORS ARE MODIFIED BY ONE CONSTANT AMOUNT AND THE ADDRESS VALUES FROM THE OTHER PROCESSOR ARE MODIFIED BY ANOTHER CONSTANT AMOUNT TO PRODUCE MUTUALLY EXCLUSIVE ADDRESS VALUES. PREFERABLY, THE MODIFIED ADDRESS VALUES ARE COMPARED WITH A LIMIT VALUE PRIOR TO THE INITIATION OF THE MEMORY READ-WRITE CYCLE. MOST ADVANTAGEOUSLY, THE MEMORY UNIT IS DIVIDED INTO MODULES ASSIGNED TO ONE OR THE OTHER OF THE PROCESSORS AND ONLY THE PORTION OF THE MEMORY ADDRESS VALUES DESIGNATING THE MODULE ARE MODIFIED.

公开(公告)号：US3362014A

公开(公告)日：1968-01-02

申请号：US32738363

申请日：1963-12-02

Applicant: BURROUGHS CORP

Inventor： HAUCK ERWIN A

IPC: G06F5/08

CPC classification number: G06F5/08

公开(公告)号：US3629854A

公开(公告)日：1971-12-21

申请号：US3629854D

申请日：1969-07-22

Applicant: BURROUGHS CORP

Inventor： HAUCK ERWIN A ,  WERNER JOHN R

IPC: G06F13/10 ,  G06F9/46 ,  G06F13/37 ,  G06F15/16 ,  G06F15/177

CPC classification number: G06F13/37

Abstract: A computer having any number of processors of equal capability in the system, each processor being able to scan all peripheral devices over a common bus, with priority resolution being provided by connecting the processors in a closed loop on which is circulated a priority bit. Only the processor receiving the bit can utilize the common bus and circulation of the bit is interrupted by the processor utilizing the common bus.