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公开(公告)号：US06915462B1
公开(公告)日：2005-07-05
申请号：US10209552
申请日：2002-07-30
IPC分类号： G11B20/20
CPC分类号： G11B20/20
摘要： An invention is provided for a deskewer that corrects skew on a data channel. The deskewer includes a delay calculator that calculates deskew data indicating the amount of delay needed to correct skew on a data channel. Coupled to the delay calculator is a deskew circuit that receives the deskew data from the delay calculator and uses the deskew data to delay a bit stream on the data channel.
摘要翻译： 提供了一种用于校正数据信道上的偏斜的偏移台的发明。 该台式电脑包括一个延迟计算器，该延迟计算器计算指示在数据通道上纠正偏斜所需的延迟量的偏斜数据。 耦合到延迟计算器是从延迟计算器接收偏斜数据并使用偏斜数据来延迟数据信道上的比特流的偏斜电路。
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公开(公告)号：US07324421B1
公开(公告)日：2008-01-29
申请号：US10218313
申请日：2002-08-13
IPC分类号： G11B11/00
CPC分类号： H03K5/135 , H04L7/0337
摘要： An invention is provided for data bit align. The invention includes a multiplexer that receives a data sample word as data input and also receives a clock sample word as select input. The multiplexer selects a data bit from the data sample word based on the clock sample word. Generally, the multiplexer can select the data bit from the data sample word corresponding to a position of the clock edge in the clock sample word. The invention also includes an output register, which is coupled to the multiplexer. The output register stores the selected data bit from the multiplexer and provides the selected data bit to remaining system components.
摘要翻译： 提供了一种用于数据位对齐的发明。 本发明包括接收数据采样字作为数据输入并且还接收时钟采样字作为选择输入的多路复用器。 多路复用器根据时钟采样字从数据采样字中选择一个数据位。 通常，多路复用器可以从对应于时钟采样字中的时钟沿的位置的数据采样字中选择数据位。 本发明还包括耦合到多路复用器的输出寄存器。 输出寄存器从多路复用器存储所选择的数据位，并将选定的数据位提供给剩余的系统组件。
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公开(公告)号：US06981185B1
公开(公告)日：2005-12-27
申请号：US10215919
申请日：2002-08-09
CPC分类号： H03K5/1565
摘要： An apparatus for correcting duty cycle error is provided which includes circuitry capable of determining existence of a duty cycle error from input data received over data transmissions lines where the circuitry generates duty cycle correction data based on the duty cycle error. The apparatus also includes a digital analog converter (DAC) being coupled to the circuitry where the DAC is capable of receiving a magnitude portion of the duty cycle correction data from the circuitry. The apparatus further includes an adjustable bias driver being coupled to the circuitry, the DAC and the data transmission lines. The adjustable bias driver receives the magnitude portion of the duty cycle correction data from the DAC and receives a polarity portion of the duty cycle correction data from the circuitry where the adjustable bias driver adjusts the polarity of signals applied to the data transmission lines for correcting the duty cycle error.
摘要翻译： 提供了一种用于校正占空比误差的装置，其包括能够基于通过数据传输线路接收的输入数据来确定占空比误差的存在的电路，其中电路基于占空比误差产生占空比校正数据。 该装置还包括耦合到电路的数字模拟转换器（DAC），其中DAC能够从电路接收占空比校正数据的幅度部分。 该装置还包括耦合到电路，DAC和数据传输线的可调节偏置驱动器。 可调偏置驱动器从DAC接收占空比校正数据的大小部分，并从电路接收占空比校正数据的极性部分，其中可调偏置驱动器调节施加到数据传输线的信号的极性，以校正 占空比误差。
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公开(公告)号：US07206798B1
公开(公告)日：2007-04-17
申请号：US10209494
申请日：2002-07-30
申请人： Barry Allen Davis
发明人： Barry Allen Davis
IPC分类号： G06F17/10
CPC分类号： H03H17/0261
摘要： The present invention provides a dual stage digital filter and a method for filtering digital data signals. The dual stage digital filter includes a pre-filter, a main filter, and an output register. The pre-filter receives a set of first data bits as inputs and is arranged to filter single noise bits from the set of input data bits to output a set of second data bits. The main filter is coupled to receive the set of second data bits as inputs and is arranged to filter burst noise bits from the set of second data bits to output a set of third data bits. The output register is coupled to receive and store the set of third data bits for output.
摘要翻译： 本发明提供了一种双级数字滤波器和一种用于对数字数据信号进行滤波的方法。 双级数字滤波器包括预滤波器，主滤波器和输出寄存器。 预滤波器接收一组第一数据比特作为输入，并且被布置为从输入数据比特组中滤除单个噪声比特以输出一组第二数据比特。 主滤波器被耦合以接收该组第二数据比特作为输入，并且被布置为从该组第二数据比特中滤出突发噪声比特以输出一组第三数据比特。 输出寄存器被耦合以接收和存储用于输出的第三数据位的集合。
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