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公开(公告)号：US20180315376A1
公开(公告)日：2018-11-01
申请号：US15740300
申请日：2017-06-28
发明人： Mo CHEN , Xiong XIONG , Jilei GAO , Songmei SUN
IPC分类号： G09G3/3258 , G09G3/3233 , G09G3/3266 , G09G3/3291 , H01L27/32
摘要： Disclosed is a pixel driving circuit, comprising a driving control circuit, a first driving circuit and a second driving circuit. The driving control circuit is configured to control one of the first driving circuit and the second driving circuit to be turned on under the condition the first scanning line outputs an effective voltage signal, and control the other of the first driving circuit and the second driving circuit to be turned on under the condition the second scanning line outputs an effective voltage signal. The first driving circuit is configured to drive the light emitting circuit to emit light under control of the driving control circuit. The second driving circuit is configured to drive the light emitting circuit to emit light under control of the driving control circuit.
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公开(公告)号：US20190318796A1
公开(公告)日：2019-10-17
申请号：US16244499
申请日：2019-01-10
发明人： Xiong XIONG , Xiaozhe ZHANG , Yudong LIU , Jianjun WANG
摘要： A shift register unit is provided, which includes an input circuit, a first output circuit and a first output signal adjustment circuit. The input circuit is configured for receiving an input signal from an input terminal and controlling an electrical signal of a first node based on the input signal. The first output circuit is configured for outputting a first output signal at a first output terminal of the shift register unit based on a first clock signal under control of the electrical signal of the first node. The first output signal adjustment circuit is configured for providing a first reference signal to the first output terminal under control of the second clock signal so as to decrease an amplitude of the first output signal.
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3.发明申请公开(公告)号：US20170200831A1
公开(公告)日：2017-07-13
申请号：US15325488
申请日：2016-05-20
发明人： Yudong LIU , Xiong XIONG , Chengying CAO , Hui WANG , Lin LIN , Fangfang WU
IPC分类号： H01L29/786 , H01L29/423 , H01L29/417
CPC分类号： H01L29/78618 , H01L27/1218 , H01L27/124 , H01L29/41733 , H01L29/4236 , H01L29/42384 , H01L29/78603
摘要： The present disclosure provides a thin-film transistor. The thin-film transistor includes a substrate including at least one trench; at least one electrode in each of the at least one trench, the at least one electrode being one or more of a gate electrode, a source electrode, and a drain electrode; and an active layer over the at least one electrode.
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公开(公告)号：US20200218316A1
公开(公告)日：2020-07-09
申请号：US15751573
申请日：2017-08-01
发明人： Xiaozhe ZHANG , Guohua WANG , Xiong XIONG
IPC分类号： G06F1/18 , G02F1/1339 , G02F1/1335
摘要： The present disclosure provides a display substrate, a method for preparing the same, and a display motherboard. The display substrate comprises: a plurality of display areas spaced apart from each other, each of which is provided with a plurality of spacers; and a blank area between any two adjacent display areas of the plurality of display areas, and provided with a plurality of supporters having the same material and height as the spacers. Since the blank area is provided with the supporters in the display substrate of this disclosure, the problem with uneven cell gap between the blank area and the display area under an action of atmospheric pressure is effectively avoided, thereby preventing the phenomenon that the display motherboard at a place with a greater cell gap presents a yellow color when displaying.
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公开(公告)号：US20210358385A1
公开(公告)日：2021-11-18
申请号：US16624102
申请日：2019-08-06
发明人： Xiong XIONG , Yifeng ZOU , Yudong LIU , Youlu LI
IPC分类号： G09G3/20
摘要： A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.
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6.发明申请公开(公告)号：US20190213970A1
公开(公告)日：2019-07-11
申请号：US16179671
申请日：2018-11-02
发明人： Zixuan WANG , Peng CHEN , Tong YANG , Xianrui QIAN , Yuting CHEN , Suzhen MU , Zhou RUI , Xiong XIONG
CPC分类号： G09G3/3677 , G09G2310/0286 , G09G2310/06 , G09G2320/0257 , G11C19/28
摘要： A shift register circuit includes a pull-up control sub-circuit, a pull-up sub-circuit and a shutdown auxiliary sub-circuit. The pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under the control of the voltage from the signal input terminal. The shut-down auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under the control of a voltage from the pull-up node. The pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under the control of a voltage from the pull-up node. The first signal output terminal is configured to be connected to a gate line.
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