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1.发明授权Apparatus and method for expediting subtraction procedures in a carry/save adder multiplication unit 失效用于在进位/保存加法器乘法单元中加速减法程序的装置和方法
公开(公告)号：US4862405A
公开(公告)日：1989-08-29
申请号：US68262
申请日：1987-06-30
CPC分类号： G06F7/5312
摘要： In a multiplier unit implemented with carry/save adder stages and executing a modified Booth algorithm, the signals, required to complete the 2's complement in order to perform a subtraction operation during the multiplication procedure using carry/save adder cells, are entered in the first carry/save stage in the appropriate carry/save cell positions. In this manner, one less signal is processed by the time-critical least significant cell associated with each carry/save adder stage, thereby reducing the overall time delay associated with the multiplier unit and accelerating the multiplication operation.
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