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    Stacking series of non-power-of-two frame buffers in a memory array
    1.
    发明申请
    Stacking series of non-power-of-two frame buffers in a memory array 有权
    在存储器阵列中堆叠两个非功率的两帧缓冲器

    公开(公告)号：US20070013705A1

    公开(公告)日：2007-01-18

    申请号：US11179221

    申请日：2005-07-11

    申请人： Bradley Roach ,  Raul Oteyza ,  David Duckman

    发明人： Bradley Roach ,  Raul Oteyza ,  David Duckman

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0223

    摘要： Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

    摘要翻译： 公开了当帧大小不是两倍的字节数时，将数据帧存储在帧缓冲器中，其大小适合于帧大小。 缓冲区大小选择为小于帧大小的最大二次幂。 当要存储数据帧时，可以将缓冲器数量乘以缓冲器大小以获得部分帧缓冲器地址Q.从帧大小中减去的缓冲器大小被称为剩余缓冲器大小， 并且缓冲器数量被有效地乘以残余缓冲器大小以获得残余帧缓冲器地址R.全帧缓冲器起始地址S = Q + R。 对于帧大小和缓冲器大小之间的差异是二分之一值的实现，可以使用二进制移位和相加来代替乘法器。

    Queuing fibre channel receive frames
    2.
    发明授权
    Queuing fibre channel receive frames 有权
    排队光纤通道接收帧

    公开(公告)号：US06728861B1

    公开(公告)日：2004-04-27

    申请号：US10382728

    申请日：2003-03-04

    申请人： Bradley Roach ,  Raul Oteyza ,  Karl M. Henson

    发明人： Bradley Roach ,  Raul Oteyza ,  Karl M. Henson

    IPC分类号： G06F1206

    CPC分类号： H04L47/50

    摘要： A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.

    摘要翻译： 帧接收队列可以对由光纤通道网络中的节点接收的帧执行反汇编和验证操作。 帧接收队列可以存储用于稍后处理帧的信息，例如头部数据和前八个有效载荷字，用于快速处理器访问。 帧的有效载荷数据可以存储在较大的外部存储器中。

    Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
    3.
    发明授权
    Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes 有权
    锁相环（PLL）电路，用于选择性地校正不同模式下的时钟偏移

    公开(公告)号：US07227921B2

    公开(公告)日：2007-06-05

    申请号：US10379776

    申请日：2003-03-03

    申请人： Jim Butler ,  Raul Oteyza

    发明人： Jim Butler ,  Raul Oteyza

    IPC分类号： H03D3/24 ,  H03L7/06

    CPC分类号： G06F1/10 ,  H03L7/06

    摘要： A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.

    摘要翻译： 锁相环（PLL）电路包括多个可选反馈路径和用于在不同操作模式中选择不同反馈路径的模式选择器。 在不同的工作模式下，PLL电路可以校正时钟偏移或在输入和输出时钟信号之间产生期望的时钟偏差程度。

    Variable access fairness in a fibre channel arbitrated loop
    5.
    发明授权
    Variable access fairness in a fibre channel arbitrated loop 失效
    光纤通道仲裁环路中的可变访问公平性

    公开(公告)号：US06459701B1

    公开(公告)日：2002-10-01

    申请号：US09370096

    申请日：1999-08-06

    申请人： Karl Henson ,  Raul Oteyza

    发明人： Karl Henson ,  Raul Oteyza

    IPC分类号： H04L1228

    CPC分类号： H04L12/433

    摘要： A method whereby a fair port in a Fibre Channel Arbitrated Loop behaves unfairly during portions of its loop tenancy and behaves fairly during other portions. In a preferred implementation, the fair port establishes a first loop circuit with an initial destination port during a loop tenancy. Before relinquishing control of the loop to an arbitrating port, the fair port—under the control of a transfer protocol—establishes one or more subsequent loop circuits with other destination ports. Loop circuits are established in sequence without the fair port relinquishing control of the loop and rearbitrating. This continues until (1) the fair port establishes a loop circuit with every destination port to which it desires to exchange information; (2) a fixed time period has lapsed; and/or (3) a predefined maximum number of loop circuits are established.

    摘要翻译： 光纤通道仲裁环中的公平端口在其循环租赁的部分期间不公平地执行的方法，并且在其他部分期间相当地表现。 在优选实施例中，公平端口在循环租赁期间建立具有初始目的地端口的第一回路电路。 在将循环控制放弃到仲裁端口之前，在传输协议控制下的公平端口与其他目的端口建立一个或多个后续环路电路。 循环电路按顺序建立，没有公平的端口放弃环路和后置位的控制。 这样一直持续到（1）公平港口与其希望交换信息的每个目的港口建立回路电路; （2）固定时间段已经过去了; 和/或（3）建立预定的最大数量的环路电路。