公开(公告)号：US06901516B1

公开(公告)日：2005-05-31

申请号：US09244203

申请日：1999-02-04

申请人： Brett Howard ,  Peter Selwyn ,  Shawn Lennox ,  Clayton Cameron ,  Michel Lamarche ,  Lorne Flindall ,  Andrew Robison ,  Wajdi Feghali

发明人： Brett Howard ,  Peter Selwyn ,  Shawn Lennox ,  Clayton Cameron ,  Michel Lamarche ,  Lorne Flindall ,  Andrew Robison ,  Wajdi Feghali

IPC分类号： H04L12/24 ,  H04L29/06 ,  H04L9/00

CPC分类号： H04L41/0893 ,  H04L41/12 ,  H04L63/0272 ,  H04L63/0435 ,  H04L63/0823 ,  H04L63/083 ,  H04L63/102 ,  H04L63/123 ,  H04L63/20 ,  Y10S370/911

摘要： A system for ciphering data for transmission by a communication device is provided. The system includes a memory device having a memory buffer a first access port connected to the memory buffer and a second access port connected to the memory buffer. The system also has a data processing processor connected to the first access port via a first bus and a ciphering processor connected to the second access port via a second bus. The first access port and the second access port each provide mutually independent access to the memory buffer. The second bus is not connected to the first bus. The data processing processor is adapted to receive the data and provide the data to the memory buffer over the first bus. The ciphering processor is adapted to retrieve the data from the memory buffer over the second bus, generate ciphered data from the data, generate integrity check information for the ciphered data using the data and provide the ciphered data to the memory buffer over the second bus.

摘要翻译： 提供一种用于加密由通信设备传输的数据的系统。 该系统包括具有存储器缓冲器的存储器件，连接到存储器缓冲器的第一访问端口和连接到存储器缓冲器的第二访问端口。 该系统还具有通过第一总线连接到第一接入端口的数据处理处理器和经由第二总线连接到第二接入端口的加密处理器。 第一访问端口和第二访问端口各自提供对存储器缓冲器的相互独立的访问。 第二个总线未连接到第一个总线。 数据处理处理器适于接收数据并通过第一总线将数据提供给存储器缓冲器。 加密处理器适于通过第二总线从存储器缓冲器检索数据，从数据生成加密数据，使用数据生成加密数据的完整性检查信息，并通过第二总线将加密数据提供给存储器缓冲器。

公开(公告)号：US20140095845A1

公开(公告)日：2014-04-03

申请号：US13631807

申请日：2012-09-28

申请人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

发明人： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Kirk Yap

IPC分类号： G06F9/30

摘要： An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

摘要翻译： 描述了一种用于在流水线处理器中执行有效的布尔运算的装置和方法，其在一个实施例中不本地支持三个操作数指令。 例如，根据本发明的一个实施例的处理器包括：一组用于存储打包操作数的寄存器; 用于执行单个指令的布尔运算逻辑，其使用打包在该组寄存器中的三个或更多个源操作数，布尔运算逻辑读取至少三个源操作数，并且立即值对三个源操作数执行布尔运算，其中， 布尔操作包括：组合从三个操作数中的每一个读取的位以形成立即值的索引，该索引标识立即值内的位位置; 从识别的位置读取该位从立即值; 并将来自所识别的立即值的比特位置的比特存储在目的地寄存器中。

公开(公告)号：US08041945B2

公开(公告)日：2011-10-18

申请号：US12455038

申请日：2009-05-27

申请人： Jaroslaw J. Sydir ,  Kamal J. Koshy ,  Wajdi Feghali ,  Bradley A. Burres ,  Gilbert M. Wolrich

发明人： Jaroslaw J. Sydir ,  Kamal J. Koshy ,  Wajdi Feghali ,  Bradley A. Burres ,  Gilbert M. Wolrich

IPC分类号： H04L29/06

CPC分类号： H04L63/0485 ,  H04L9/0643 ,  H04L63/12 ,  H04L2209/125

摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.

摘要翻译： 描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理 数据包

公开(公告)号：US07961877B2

公开(公告)日：2011-06-14

申请号：US11610886

申请日：2006-12-14

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

IPC分类号： H04L9/30 ,  H04L9/28 ,  H04L9/00 ,  G06G7/16

CPC分类号： G06F7/723

摘要： The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段，并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20100153829A1

公开(公告)日：2010-06-17

申请号：US12336029

申请日：2008-12-16

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

IPC分类号： H03M13/09 ,  G06F7/72 ,  G06F11/10

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

公开(公告)号：US07607068B2

公开(公告)日：2009-10-20

申请号：US11469222

申请日：2006-08-31

申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Wajdi Feghali ,  Robert P. Ottavi

发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Wajdi Feghali ,  Robert P. Ottavi

IPC分类号： G11C29/00

CPC分类号： G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。 一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间​​输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20080159528A1

公开(公告)日：2008-07-03

申请号：US11617418

申请日：2006-12-28

申请人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

发明人： Wajdi Feghali ,  Stephanie Hirnak ,  Makaram Raghunandan ,  Yogesh Bansal ,  Kirk Yap ,  Gilbert M. Wolrich

IPC分类号： H04L9/30 ,  H04L9/28

CPC分类号： H04L63/0485 ,  G06F9/30181 ,  G06F9/3879 ,  H04L63/08

摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。 根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。 该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。 该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。 该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20080148011A1

公开(公告)日：2008-06-19

申请号：US11610897

申请日：2006-12-14

申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Gunnar Gaubatz ,  Daniel Cutter ,  Wajdi Feghali ,  Kaan Yuksel ,  Erdinc Ozturk

发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Gunnar Gaubatz ,  Daniel Cutter ,  Wajdi Feghali ,  Kaan Yuksel ,  Erdinc Ozturk

IPC分类号： G06F9/30

CPC分类号： G06F9/3001

摘要： The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了用于执行进位/借用处理的系统和方法。 根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。 该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。 该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20080144811A1

公开(公告)日：2008-06-19

申请号：US11610919

申请日：2006-12-14

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Kaan Yuskel ,  Gunnar Gaubatz ,  Wajdi Feghali ,  Gilbert M. Wolrich

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Kaan Yuskel ,  Gunnar Gaubatz ,  Wajdi Feghali ,  Gilbert M. Wolrich

IPC分类号： H04L9/30

CPC分类号： G06F7/723 ,  H04L9/302

摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种用于执行模幂运算的方法。 该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q） ）。 该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数 第二余数（xq）升至第二素数（q）的第二私钥号（d2）。 该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。 该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。 该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20050149744A1

公开(公告)日：2005-07-07

申请号：US10749913

申请日：2003-12-29

申请人： Jaroslaw Sydir ,  Kamal Koshy ,  Wajdi Feghali ,  Bradley Burres ,  Gilbert Wolrich

发明人： Jaroslaw Sydir ,  Kamal Koshy ,  Wajdi Feghali ,  Bradley Burres ,  Gilbert Wolrich

IPC分类号： G06F21/00 ,  H04L9/32 ,  H04L29/06

CPC分类号： H04L63/0428 ,  G06F21/72 ,  H04L9/32 ,  H04L63/08

摘要： A network processing having cryptographic processing includes an authentication buffer for storing ciphered data and providing the ciphered data to an authentication core.

摘要翻译： 具有加密处理的网络处理包括用于存储加密数据并将加密数据提供给认证核心的认证缓冲器。