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公开(公告)号：US5619627A
公开(公告)日：1997-04-08
申请号：US237285
申请日：1994-05-03
CPC分类号： G06T15/40
摘要： Occulting apparatus for use with an image generator that provides for multiple-level occulting of image data. The occulting apparatus comprises a mask buffer and control logic for processing image data to construct and store an obscurance mask in the mask buffer. Foreground entities contained in the image data are logically ORed into the mask buffer until the entities extend beyond a predefined range from a predetermined image viewpoint. Thereafter, the mask is used by the control logic to reject entities contained in subsequently processed image data that are fully obscured by the foreground entities comprising the obscurance mask. The control logic includes an obscurance manager, a region processor, an object processor, a polygon processor, and insertion logic. The obscurance manager is a controller for building and applying the obscurance mask to the image data. The region, object, and polygon processors respectively process regions, objects, and polygons in the image to determine if they are obscured, reject obscured entities, and transmits unobscured entities to subsequent processors. The insertion logic processes unobscured polygons and applies them to the obscurance manager for storage and use by the respective region, object, and polygon processors. The present invention performs real-time occulting of all objects in an image scene, whether they are fixed or moving. Hidden area modules (large groups of objects in a geographic region), single objects, polygons, and pixels are sequentially filtered-out in real-time. The mask buffer and control logic provide three levels of occulting. A hybrid Z-buffer 51 provides pixel-level occulting. The present invention rejects regions, objects, and polygons, early in the graphics processing pipeline to reduce the number of required pixel processing computational elements in the image generator. By rendering objects generally from front to back, entities that are completely hidden by nearer objects can be detected and discarded before tiling and pixel processing.
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2.发明授权
公开(公告)号：US5493643A
公开(公告)日：1996-02-20
申请号：US237286
申请日：1994-05-03
申请人： Brian T. Soderberg , Dale D. Miller , Douglas Pheil , Kent Cauble , Mark N. Heinen , Mark L. Kenworthy
发明人： Brian T. Soderberg , Dale D. Miller , Douglas Pheil , Kent Cauble , Mark N. Heinen , Mark L. Kenworthy
CPC分类号： G06T1/20 , G06T15/005 , G09B9/003 , G09B9/301
摘要： An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing. At this level, the displayed image is divided into small sub-regions that are assigned to tilers in a pseudo-random, but fixed manner. This levels the load across all pixel processors. Typically, tilers process a large contiguous area of the image. The present invention uses small sub-regions (64.times.64 pixels) and assigns many sub-regions from different channels to a single tiler. Each tiler maintains equal loading .even with localized regions of high pixel processing. The third level relates to two-by-two pixel, fixed interleave processing. The image is further divided into 2.times.2 pixel blocks spread across multiple pixel operators on a tiler. This fine grain parallelism, in a fixed pseudo-random orientation, ensures equal loading across all pixel processors. The second aspect of the present invention is the use of polygon and pixel distribution buses. Maximum image generator configurability, expansion, and efficient processing is required for a variety of simulator configurations used in networked training environments. To accomplish this, distribution buses are implemented between all graphics processing stages.
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公开(公告)号：US5471567A
公开(公告)日：1995-11-28
申请号：US741999
申请日：1991-08-08
CPC分类号： G06T15/503
摘要： Depth buffered anti-aliasing in a real time image generation system utilizing two separate buffers, one for combining attributes of object pixel definitions which are of less than full coverage and another for storing the attributes of each new object pixel definition which is of full coverage and which is closer to the viewpoint than any attributes currently stored. If the depth value in the partial buffer is closer the viewpoint than that in the full buffer, a set of attributes is output which is a weighted mixture of those stored in the two buffers.
摘要翻译： 利用两个单独的缓冲器的实时图像生成系统中的深度缓冲的抗混叠，一个用于组合小于全覆盖的对象像素定义的属性，另一个用于存储全覆盖的每个新对象像素定义的属性， 它比当前存储的任何属性更接近视点。 如果部分缓冲器中的深度值比全缓冲器中的深度值更接近，则输出一组属性，这是存储在两个缓冲器中的那些属性的加权混合。
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