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公开(公告)号：US07237094B2
公开(公告)日：2007-06-26
申请号：US10965143
申请日：2004-10-14
申请人： Brian William Curran , Brian R. Konigsburg , Hung Qui Le , David Arnold Luick , Dung Quoc Nguyen
发明人： Brian William Curran , Brian R. Konigsburg , Hung Qui Le , David Arnold Luick , Dung Quoc Nguyen
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/382 , G06F9/3851 , G06F9/3885
摘要： A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.
摘要翻译： 通过将资源字段与相应的程序指令相关联来处理计算机处理器中的指令的更有效的方法，其中资源字段指示需要哪个处理器硬件资源来执行程序指令，计算用于合并两个或多个程序指令的资源需求 并且基于所计算的资源需求来确定用于同时执行所合并的程序指令的资源可用性。 指示所需资源的资源矢量可以被编码到资源字段中，并且在稍后阶段解码资源字段以导出资源向量。 资源字段可以存储在与相应的程序指令相关联的指令高速缓存中。 处理器可以以同时多线程模式操作，其中不同的程序指令是不同硬件线程的一部分。 当资源可用性等于或超过一组指令的资源需求时，可以将这些指令同时发送到硬件资源。 可以在程序指令之一中插入起始位以定义指令组。 硬件资源可以特别地是诸如定点单元，加载/存储单元，浮点单元或分支处理单元之类的执行单元。
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2.发明申请INVERTING DATA ON RESULT BUS TO PREPARE FOR INSTRUCTION IN THE NEXT CYCLE FOR HIGH FREQUENCY EXECUTION UNITS 失效在高频执行单位的下一个周期中，将结果总线上的数据反转为准备指令公开(公告)号：US20080301411A1
公开(公告)日：2008-12-04
申请号：US12189797
申请日：2008-08-12
CPC分类号： G06F9/3001 , G06F9/3867
摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
摘要翻译： 一种通过使来自指令解码逻辑的控制信号反应在当前周期期间执行的操作的结果来操作算术逻辑单元（ALU）的方法，其指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。
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公开(公告)号：US5765207A
公开(公告)日：1998-06-09
申请号：US768048
申请日：1996-12-16
申请人： Brian William Curran
发明人： Brian William Curran
IPC分类号： G06F12/10
CPC分类号： G06F12/10
摘要： A state machine computing system provides multiple state registers, a recursive hardware state machine computing system; particularly address translation hardware which can be used in multiprocessors, parallel machines and massively parallel machines. The hardware state machine includes a mechanism to push values into a state register stack and to pop values from the state register stack. The stack consists of a plurality of state registers, one of which is designated the current state register and the remainder designated as prior (or saved) state registers. Recursive logic is provided to increment the current state register. The recursive state machine described provides significant advantages over prior art hardware implementations of guest virtual address translation because guest virtual address translations recursively invoke host virtual address translation.
摘要翻译： 状态机计算系统提供多个状态寄存器，递归硬件状态机计算系统; 特别是可用于多处理器，并行机器和大型并行机器的地址转换硬件。 硬件状态机包括将值推入状态寄存器堆栈并从状态寄存器堆栈弹出值的机制。 堆栈由多个状态寄存器组成，其中一个状态寄存器被指定为当前状态寄存器，其余指定为先前（或保存）状态寄存器。 提供递归逻辑来增加当前的状态寄存器。 所描述的递归状态机提供了优于客体虚拟地址转换的现有技术硬件实现的显着优点，因为访客虚拟地址转换递归地调用主机虚拟地址转换。
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4.发明授权Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units 失效在结果总线上反转数据，准备高频执行单元下一个周期的指令公开(公告)号：US07509365B2
公开(公告)日：2009-03-24
申请号：US11056894
申请日：2005-02-11
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/3867
摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
摘要翻译： 一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。
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公开(公告)号：US5771369A
公开(公告)日：1998-06-23
申请号：US474016
申请日：1995-06-07
申请人： Brian William Curran
发明人： Brian William Curran
IPC分类号： G06F12/02 , G11C8/00 , G11C11/401 , G11C11/408 , G06F12/06
CPC分类号： G11C11/408 , G06F12/0215 , G11C8/00
摘要： Improved memory access is provided for use when addressing dynamic random access modules (DRAMs). Both the memory contoller and the main memory hardware remember the row address of the last access. The main memory hardware redrives that row address to the DRAMs after completion of an access.
摘要翻译： 提供了改进的存储器访问，用于寻址动态随机存取模块（DRAM）。 存储器轮廓器和主存储器硬件都记住最后访问的行地址。 完成访问后，主存储器硬件将行地址重新发送到DRAM。
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6.发明授权Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units 失效在结果总线上反转数据，准备高频执行单元下一个周期的指令公开(公告)号：US07991816B2
公开(公告)日：2011-08-02
申请号：US12189797
申请日：2008-08-12
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F9/3867
摘要： A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
摘要翻译： 一种通过将当前周期内要执行的操作的结果与来自指令解码逻辑的控制信号相反的操作算术逻辑单元（ALU）的方法，该指令解码逻辑指示稍后的操作将需要结果的补码，其中， 结果在当前周期内反转。 稍后的操作可以是紧跟在第一操作之后的减法操作。 后续指令在当前周期之前进行解码，以控制ALU中的反转。 ALU包括加法器，旋转器和数据操作单元，其响应于反转控制信号在当前周期内反转结果。 第二操作在随后的周期中减去结果，其中使能到加法器的进位控制信号，并且旋转器和数据操作单元被禁用。 ALU可以用在诸如定点单元的微处理器的执行单元中。
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公开(公告)号：US07904697B2
公开(公告)日：2011-03-08
申请号：US12044013
申请日：2008-03-07
CPC分类号： G06F9/30032 , G06F9/384
摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.
摘要翻译： 一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。 在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。 当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。 并且通过这个任务，别名被破坏了。 类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。 并且通过这个任务，别名被破坏了。
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公开(公告)号：US20090228692A1
公开(公告)日：2009-09-10
申请号：US12044013
申请日：2008-03-07
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/384
摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.
摘要翻译： 一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。 在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。 当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。 并且通过这个任务，别名被破坏了。 类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。 并且通过这个任务，别名被破坏了。
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公开(公告)号：US6104212A
公开(公告)日：2000-08-15
申请号：US21868
申请日：1998-02-11
申请人： Brian William Curran
发明人： Brian William Curran
IPC分类号： H03K19/096 , H03K19/094
CPC分类号： H03K19/0963
摘要： A domino CMOS circuit has a number of domino gates, a common virtual ground node and a common evaluation NFET device. Each domino gate provides a PFET precharge device, an NFET device tree, an output inverter stage, a dynamic node, a plurality of input nodes, a clock input node and an output node. The PFET precharge device is coupled to a high voltage supply rail, the clock input node and the dynamic node and an NFET device tree is coupled to the common virtual ground node, to the plurality of inputs and to the dynamic node. An output inverter stage is coupled to the high voltage supply rail, to said dynamic node, to a low voltage supply rail and to said output node. And for improving performance, a common evaluation NFET device is coupled to said clock inputnode, to the to said low voltage supply rail and to the common virtual ground node. The virtual ground node is coupled to the low voltage supply rail when a high voltage is applied to clock input node.
摘要翻译： 多米诺CMOS电路具有多个多米诺门，一个通用虚拟接地节点和一个通用的评估NFET器件。 每个多米诺骨门提供PFET预充电器件，NFET器件树，输出反相器级，动态节点，多个输入节点，时钟输入节点和输出节点。 PFET预充电装置耦合到高电压电源轨，时钟输入节点和动态节点，并且NFET器件树耦合到公共虚拟接地节点，耦合到多个输入端和动态节点。 输出反相级与高电压电源轨，所述动态节点耦合到低电压电源轨和所述输出节点。 为了提高性能，公共评估NFET器件耦合到所述时钟输入节点，耦合到所述低电压电源轨和公共虚拟接地节点。 当高电压施加到时钟输入节点时，虚拟接地节点耦合到低电压电源轨。
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