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1.发明申请公开(公告)号：US20190115933A1
公开(公告)日：2019-04-18
申请号：US16153474
申请日：2018-10-05
摘要： An acceleration apparatus applied in an artificial neuron is disclosed. The acceleration apparatus comprises an AND gate array, a first storage device, a second storage device and a multiply-accumulate (MAC) circuit. The AND gate array with plural AND gates receives a first bitmap and a second bitmap to generate an output bitmap. The first storage device stores a first payload and outputs a corresponding non-zero first element according to a first access address associated with a result of comparing the first bitmap with the output bitmap. The second storage device stores a second payload and outputs a corresponding non-zero second element according to a second access address associated with a result of comparing the second bitmap with the output bitmap. The MAC circuit calculates a dot product of two element sequences from the first storage device and the second storage device.
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公开(公告)号：US11379714B2
公开(公告)日：2022-07-05
申请号：US16425244
申请日：2019-05-29
发明人： Chi-Wei Peng , Wei-Hsiang Tseng , Hong-Ching Chen , Shen-Jui Huang , Meng-Hsun Wen , Yu-Pao Tsai , Hsuan-Yi Hou , Ching-Hao Yu , Tsung-Liang Chen
IPC分类号： G06N3/06 , G11C11/41 , G06N3/063 , G11C11/413 , H03M1/82
摘要： An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.
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公开(公告)号：US11501135B2
公开(公告)日：2022-11-15
申请号：US16407222
申请日：2019-05-09
发明人： Meng-Hsun Wen , Cheng-Chih Tsai , Jen-Feng Li , Hong-Ching Chen , Chen-Chu Hsu , Tsung-Liang Chen
摘要： There is provided a smart engine including a profile collector and a main processing module. The profile collector is configured to store a plurality of profiles, one or more suitable profiles being dynamically selected according to an instruction from a user or an automatic selector. The main processing module is connected to the profile collector and directly or indirectly connected to a sensor, and configured to perform a detailed analysis to determine detailed properties of features, objects, or scenes based on suitable sensor data from the sensor.
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公开(公告)号：US11594244B2
公开(公告)日：2023-02-28
申请号：US16871587
申请日：2020-05-11
IPC分类号： G10L25/78 , G10L15/06 , G10L15/16 , G06N3/08 , G06N20/10 , G10L15/02 , G10L25/87 , G10L25/84
摘要： A voice event detection apparatus is disclosed. The apparatus comprises a vibration to digital converter and a computing unit. The vibration to digital converter is configured to convert an input audio signal into vibration data. The computing unit is configured to trigger a downstream module according to a sum of vibration counts of the vibration data for a number X of frames. In an embodiment, the voice event detection apparatus is capable of correctly distinguishing a wake phoneme from the input vibration data so as to trigger a downstream module of a computing system. Thus, the power consumption of the computing system is saved.
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公开(公告)号：US11068775B2
公开(公告)日：2021-07-20
申请号：US15910404
申请日：2018-03-02
摘要： A processing apparatus applied in an artificial neuron is disclosed. The processing apparatus comprises a parser, a lookup array, a summing circuit and a MAC circuit. The parser parses one of M packets to extract a non-zero weight value from a header of the one packet, to identify a plurality of bit positions with a specified digit from a payload of the one packet, and to output the non-zero weight value and the bit positions in parallel. The lookup array contains N synapse values and is indexed by the bit positions in parallel to generate a plurality of match values. The summing circuit sums up the match values to generate a sum value. The MAC circuit generates a product of the non-zero weight value and the sum value, and generates an accumulate value based on the product and at least one previous accumulate value.
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