公开(公告)号：US09578139B2

公开(公告)日：2017-02-21

申请号：US14035293

申请日：2013-09-24

Applicant: Broadcom Corporation

Inventor： Stephane W. Rodgers

IPC: H04L29/06 ,  H04N21/426 ,  H04N21/434 ,  H04N21/44

CPC classification number: H04L69/08 ,  H04N21/42615 ,  H04N21/434 ,  H04N21/44004

Abstract: A method and system are provided for architecture of a very fast programmable transport demultiplexer using a double-buffered approach. The method may involve utilizing a hardware assist block to process incoming packets, retrieve information about the packets, and write the retrieved information to a memory block. A firmware block may then utilize the information in memory to perform further processing on the packet data. The firmware and hardware assist blocks may work simultaneously so as to speed up the processing of the packet, which can comprise record data and/or audio/video data. The system may comprise the hardware assist block, the firmware assist block, and a memory block.

Abstract translation: 提供了一种用于使用双缓冲方法的非常快速的可编程传输解复用器的架构的方法和系统。 该方法可以包括利用硬件辅助块来处理输入分组，检索关于分组的信息，以及将检索到的信息写入存储器块。 然后，固件块可以利用存储器中的信息来对分组数据执行进一步的处理。 固件和硬件辅助块可以同时工作，以加速分组的处理，其可以包括记录数据和/或音频/视频数据。 该系统可以包括硬件辅助块，固件辅助块和存储块。

公开(公告)号：US20140023093A1

公开(公告)日：2014-01-23

申请号：US14035293

申请日：2013-09-24

Applicant: Broadcom Corporation

Inventor： Stephane W. Rodgers

IPC: H04L29/06

CPC classification number: H04L69/08 ,  H04N21/42615 ,  H04N21/434 ,  H04N21/44004

Abstract: A method and system are provided for architecture of a very fast programmable transport demultiplexer using a double-buffered approach. The method may involve utilizing a hardware assist block to process incoming packets, retrieve information about the packets, and write the retrieved information to a memory block. A firmware block may then utilize the information in memory to perform further processing on the packet data. The firmware and hardware assist blocks may work simultaneously so as to speed up the processing of the packet, which can comprise record data and/or audio/video data. The system may comprise the hardware assist block, the firmware assist block, and a memory block.

Abstract translation: 提供了一种用于使用双缓冲方法的非常快速的可编程传输解复用器的架构的方法和系统。 该方法可以包括利用硬件辅助块来处理输入分组，检索关于分组的信息，以及将检索到的信息写入存储器块。 然后，固件块可以利用存储器中的信息来对分组数据执行进一步的处理。 固件和硬件辅助块可以同时工作，以加速分组的处理，其可以包括记录数据和/或音频/视频数据。 该系统可以包括硬件辅助块，固件辅助块和存储块。