公开(公告)号：US20100044797A1

公开(公告)日：2010-02-25

申请号：US12344159

申请日：2008-12-24

Applicant: Byung-Duk LEE

Inventor： Byung-Duk LEE

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66621 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/7831

Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.

Abstract translation: 具有降低的基板和插头之间的接触电阻的半导体器件包括设置在基板上的栅电极，该插塞形成在栅电极两侧的基板上并具有正斜率的侧壁，盖层设置在 栅电极和插塞，以及栅极硬掩模层，其栅极电极上方的侧壁延伸到覆盖层的顶表面。 通过使用具有负斜率的侧壁的封盖层，可以形成具有正斜率的侧壁的插塞，而不管栅电极的侧壁的形状或轮廓如何。 结果，衬底和插头之间的接触面积增加。

公开(公告)号：US20090243033A1

公开(公告)日：2009-10-01

申请号：US12344174

申请日：2008-12-24

Applicant: Byung-Duk LEE

Inventor： Byung-Duk LEE

IPC: H01L23/525 ,  H01L21/71

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.

Abstract translation: 半导体器件中的熔丝部分具有沿第一方向延伸的多条熔丝，沿着第二方向具有给定的宽度。 熔丝部分包括第一导电图案，其具有形成在衬底上的熔丝线区域中的空间部分，其中第一导电图案的部分沿着第一方向由空间部分间隔开。 熔丝部分包括形成在空间部分上的第一绝缘图案，第一绝缘图案的宽度小于第一导电图案沿着第二方向的宽度，并且厚度大于第一导电图案的厚度，第二绝缘图案 导电图案形成在第一绝缘图案上，第二导电图案的宽度大于沿着第二方向的第一绝缘图案的宽度。

公开(公告)号：US20120088361A1

公开(公告)日：2012-04-12

申请号：US13325851

申请日：2011-12-14

Applicant: Byung-Duk LEE

Inventor： Byung-Duk LEE

IPC: H01L21/768

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.

Abstract translation: 半导体器件中的熔丝部分具有沿第一方向延伸的多条熔丝，沿着第二方向具有给定的宽度。 熔丝部分包括第一导电图案，其具有形成在衬底上的熔丝线区域中的空间部分，其中第一导电图案的部分沿着第一方向由空间部分间隔开。 熔丝部分包括形成在空间部分上的第一绝缘图案，第一绝缘图案的宽度小于第一导电图案沿着第二方向的宽度，并且厚度大于第一导电图案的厚度，第二绝缘图案 导电图案形成在第一绝缘图案上，第二导电图案的宽度大于沿着第二方向的第一绝缘图案的宽度。

公开(公告)号：US20120007184A1

公开(公告)日：2012-01-12

申请号：US13237551

申请日：2011-09-20

Applicant: Byung-Duk LEE

Inventor： Byung-Duk LEE

IPC: H01L29/78

CPC classification number: H01L29/66621 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/7831

Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.

Abstract translation: 具有降低的基板和插头之间的接触电阻的半导体器件包括设置在基板上的栅电极，该插塞形成在栅电极两侧的基板上并具有正斜率的侧壁，盖层设置在 栅电极和插塞，以及栅极硬掩模层，其栅极电极上方的侧壁延伸到覆盖层的顶表面。 通过使用具有负斜率的侧壁的封盖层，可以形成具有正斜率的侧壁的插塞，而不管栅电极的侧壁的形状或轮廓如何。 结果，衬底和插头之间的接触面积增加。