公开(公告)号：US12182613B1

公开(公告)日：2024-12-31

申请号：US17245506

申请日：2021-04-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Chandra Prakash Manglani ,  Amit Khurana ,  Sunil Prasad Todi

IPC: G06F30/31 ,  G06F3/06 ,  G06F9/48

Abstract: A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.

公开(公告)号：US09875329B1

公开(公告)日：2018-01-23

申请号：US14983288

申请日：2015-12-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sunil Todi ,  Amit Khurana ,  Chandra Manglani

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A host system for transferring data to a target system is provided. The host system may include a layout database for storing mask layout data representing an integrated circuit (IC) in terms of planar geometric shapes. The hosts system may further include a processor configured to import the mask layout data from the layout database to a memory-mapped disk in the host system. The processor is further configured to translate the mask layout data into one or more cell views according to a table hierarchy in the memory-mapped disk. The processor is further configured to transmit the one or more cell views from the memory-mapped disk to a magnetic disk of the target system.