公开(公告)号：US12182613B1

公开(公告)日：2024-12-31

申请号：US17245506

申请日：2021-04-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Chandra Prakash Manglani ,  Amit Khurana ,  Sunil Prasad Todi

IPC: G06F30/31 ,  G06F3/06 ,  G06F9/48

Abstract: A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.

公开(公告)号：US10534887B1

公开(公告)日：2020-01-14

申请号：US15994255

申请日：2018-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Sravasti Nair ,  Subhashis Mandal ,  Chandra Prakash Manglani ,  Nikhil Garg ,  Preeti Kapoor ,  Kanaka Raju Gorle

IPC: G06F17/50

Abstract: A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.

公开(公告)号：US10133841B1

公开(公告)日：2018-11-20

申请号：US15282792

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Arnold Ginetti ,  Chandra Prakash Manglani ,  Amit Kumar

IPC: G06F17/50

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

公开(公告)号：US10452807B1

公开(公告)日：2019-10-22

申请号：US15476921

申请日：2017-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Karun Sharma ,  Nikhil Garg ,  Juno Jui-Chuan Lin ,  Subhashis Mandal ,  Chandra Prakash Manglani ,  Kanaka Raju Gorle ,  Henry Yu

IPC: G06F17/50

Abstract: Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.