公开(公告)号：US09710593B1

公开(公告)日：2017-07-18

申请号：US14883482

申请日：2015-10-14

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Igor Keller ,  Mikhail Chetin ,  Xiaojun Sun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031

Abstract: Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.