专利检索 ap:("CALLAHAN CELLULAR L.L.C.") AND inv:"Raminda Udaya MADURAWE" 第 1 页

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发明申请
TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC 审中-公开

公开(公告)号：US20170124241A1

公开(公告)日：2017-05-04

申请号：US15407242

申请日：2017-01-16

申请人： CALLAHAN CELLULAR L.L.C.

发明人： Raminda Udaya MADURAWE

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 , G06F17/5045 , G06F17/5077 , G06F2217/06 , G11C16/0433 , G11C17/16 , H01L27/1052 , H03K19/17796

摘要： A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.