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公开(公告)号：US20230369373A1
公开(公告)日：2023-11-16
申请号：US18356954
申请日：2023-07-21
发明人： JUNJI IWATA , KAZUHIRO MORIMOTO , YU MAEHASHI , YOSHIYUKI HAYASHI
IPC分类号： H01L27/146 , H01L31/107 , H04N25/705
CPC分类号： H01L27/14636 , H01L31/107 , H04N25/705 , H04N25/75
摘要： An apparatus includes a first substrate having a plurality of avalanche diodes, a second substrate having a plurality of pixel circuits, and a third substrate having a signal processing circuit. The second substrate and the third substrate are stacked in such a manner that a third wiring structure is provided between two semiconductor layers of the second substrate and the third substrate. The apparatus includes first through-hole wiring going through the semiconductor layer of the third substrate.
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公开(公告)号：US20240357259A1
公开(公告)日：2024-10-24
申请号：US18761033
申请日：2024-07-01
发明人： YU MAEHASHI
IPC分类号： H04N25/773 , H01L27/146 , H04N25/705 , H04N25/709 , H04N25/76 , H04N25/766 , H04N25/79
CPC分类号： H04N25/773 , H01L27/14616 , H04N25/705 , H04N25/709 , H04N25/766 , H04N25/7795 , H04N25/79
摘要： A photoelectric conversion device includes a plurality of pixels each including a photoelectric conversion unit configured to output a signal based on incidence of a photon, the photoelectric conversion unit including an avalanche photodiode configured to multiply a charge resulting from the incidence of the photon by avalanche multiplication, a processing circuit configured to process the signal output from the photoelectric conversion unit, and a pixel output circuit configured to control output of a signal processed by the processing circuit; a data line connected to the plurality of pixels; and a reception circuit configured to receive a pixel signal output from the plurality of pixels via the data line. An off-leakage current of a transistor constituting the reception circuit is lower than that of a transistor constituting the pixel output circuit.
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公开(公告)号：US20240355856A1
公开(公告)日：2024-10-24
申请号：US18762207
申请日：2024-07-02
发明人： JUNJI IWATA , KAZUHIRO MORIMOTO , YU MAEHASHI , YOSHIYUKI HAYASHI
IPC分类号： H01L27/146 , H04N25/705 , H04N25/76
CPC分类号： H01L27/14634 , H01L27/14636 , H04N25/705 , H04N25/7795
摘要： A photoelectric conversion apparatus includes a first substrate including a plurality of avalanche photodiodes, a second substrate including a plurality of pixel circuits, and a third substrate including a signal processing circuit, wherein the second substrate and the third substrate are stacked in such a manner that a third wiring structure is disposed between two semiconductor layers included in the second substrate and the third substrate, with a first through wire penetrating through the semiconductor layer included in the third substrate is disposed.
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公开(公告)号：US20230389372A1
公开(公告)日：2023-11-30
申请号：US18316488
申请日：2023-05-12
发明人： AKIHIRO KAWANO , YU MAEHASHI
IPC分类号： H10K59/127 , H10K59/131 , H10K59/80 , H10K59/12
CPC分类号： H10K59/1275 , H10K59/1201 , H10K59/873 , H10K59/131
摘要： A light-emitting device includes a structure having a first surface and a second surface opposite each other, a light-emitting portion arranged on the first surface, and a protective layer covering the light-emitting portion and the first surface. The structure further includes an electrically conductive member to which one of a signal and a potential for operating the light-emitting portion is given, and an aperture extending from the electrically conductive member to a virtual plane which includes the second surface.
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公开(公告)号：US20240355852A1
公开(公告)日：2024-10-24
申请号：US18758777
申请日：2024-06-28
发明人： KAZUHIRO MORIMOTO , JUNJI IWATA , YU MAEHASHI , HIROSHI SEKINE
IPC分类号： H01L27/146
CPC分类号： H01L27/14625 , H01L27/1462 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14643
摘要： A photoelectric conversion apparatus includes a plurality of avalanche diodes disposed in a semiconductor layer including a first surface and a second surface facing the first surface, and a first wiring structure in contact with the second surface, wherein a first pad configured to apply a first voltage to the photoelectric conversion apparatus is disposed in the first wiring structure, wherein the semiconductor layer includes a plurality of uneven structures disposed in the first surface, and wherein an effective pitch of the plurality of uneven structures is smaller than hc/Ea where h is a Planck constant [J·s], c is a speed of light [m/s], and Ea is a band gap [J] of a substrate.
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公开(公告)号：US20240255620A1
公开(公告)日：2024-08-01
申请号：US18427659
申请日：2024-01-30
发明人： YU MAEHASHI , KAZUHIRO MORIMOTO , YUJI NAKAJIMA , HIROYUKI MUTO
IPC分类号： G01S7/4863 , G01S17/931
CPC分类号： G01S7/4863 , G01S17/931
摘要： A semiconductor device includes a plurality of time-to-digital converters each including an input terminal, an output terminal, and a control terminal. A control signal line is connected to the control terminal of a first time-to-digital converter among the plurality of time-to-digital converters, the control terminal of a second time-to-digital converter among the plurality of time-to-digital converters, and the input terminal of the first time-to-digital converter. A control signal propagating through the control signal line is input to the control terminal of the second time-to-digital converter at a time later than a time when the control signal is input to the control terminal of the first time-to-digital converter, and is input to the input terminal of the first time-to-digital converter at a time later than the time when the control signal is input to the control terminal of the second time-to-digital converter.
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公开(公告)号：US20240088186A1
公开(公告)日：2024-03-14
申请号：US18459532
申请日：2023-09-01
发明人： DAIKI SHIRAHIGE , YU MAEHASHI
IPC分类号： H01L27/146
CPC分类号： H01L27/14627 , H01L27/14645
摘要： A photoelectric conversion element includes in a semiconductor layer a first semiconductor region arranged, a second semiconductor region arranged on a second face side closer than the first semiconductor region and forming a p-n junction with the first semiconductor region to form an avalanche photodiode, a light guide structure including a first portion surrounding a first region and a second portion surrounding a second region inside the first region in a plan view, and an optical structure layer disposed on the second face side. The second portion is disposed over a depth of at least 0.8 μm from the second face, the first and second semiconductor regions are arranged closer to the first face than the second portion, and the second portion overlaps at least a portion of an avalanche multiplication region between the first and second semiconductor region in the plan view.
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