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公开(公告)号：US20190086755A1
公开(公告)日：2019-03-21
申请号：US15941271
申请日：2018-03-30
发明人： Maokun TIAN , Zhonghao HUANG , Xu WU
IPC分类号： G02F1/1362 , G02F1/1333 , G02F1/1343 , H01L27/12
CPC分类号： G02F1/136286 , G02F1/133345 , G02F1/13439 , G02F2201/121 , G02F2201/123 , H01L27/124
摘要： The present disclosure provides an array substrate, a method for manufacturing the same, and a display device, which belongs to the field of display technology. The array substrate includes a metal electrode layer, a pad layer, a first insulating layer and a first transparent conductive layer, wherein: the pad layer includes a transparent conductive material, the metal electrode layer includes a conductive layer and protection layers formed on both surfaces of the conductive layer, and the pad layer is connected to the metal electrode layer; the first insulating layer is covered on the metal electrode layer and the pad layer, and the first transparent conductive layer is disposed on the first insulating layer; and a via hole is provided in the first insulating layer, and the first transparent conductive layer is connected to the pad layer through the via hole.
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公开(公告)号：US20220057679A1
公开(公告)日：2022-02-24
申请号：US17241140
申请日：2021-04-27
发明人： Maokun TIAN , Zhonghao HUANG , Xu WU , Chengjun QI , Jun WANG , Dan LIU
IPC分类号： G02F1/1362 , H01L27/12
摘要： An array substrate includes a base substrate, a light-shielding pattern, a buffer pattern, an active layer, a gate insulating layer and a first passivation layer provided with a first via, a second via and a third via, and a source and a drain. An entire orthographic projection of the active layer on the base substrate coincides with an orthographic projection of at least part of the buffer pattern on the base substrate. The orthographic projection of the buffer pattern on the base substrate is within a border of an orthographic projection of the light-shielding pattern on the base substrate, and its area is less than an area of the orthographic projection of the light-shielding pattern on the base substrate. One of the source and the drain is coupled to the active layer through the first via, and another one is coupled to the active layer through the second via and the light-shielding pattern through the third via.
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公开(公告)号：US20220293035A1
公开(公告)日：2022-09-15
申请号：US17551368
申请日：2021-12-15
发明人： Zhiyong NING , Zhonghao HUANG , Xu WU , Kunkun GAO , Chao ZHANG , Can WANG , Maokun TIAN
摘要： A shift register, a gate drive circuit, and a display panel are provided. The shift register includes an input sub-circuit configured to pre-charge a pull-up node using an input signal; an output sub-circuit configured to output a clock signal through an signal output terminal; a pull-down control sub-circuit configured to control a potential of a pull-down node using a power supply voltage signal; a first pull-down sub-circuit configured to pull down a potential of the pull-down node using a first preset voltage signal; and a first control sub-circuit configured to control the potential of the pull-up node using a second preset voltage signal in response to the potential of the pull-down node; a potential of the first preset voltage signal is lower than a potential of a non-operating level signal of the first pull-down sub-circuit, but higher than a potential of the second preset voltage signal.
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公开(公告)号：US20190101802A1
公开(公告)日：2019-04-04
申请号：US15964171
申请日：2018-04-27
发明人： Maokun TIAN , Rui WANG , Zhonghao HUANG , Wei CHEN
IPC分类号： G02F1/1362 , G02F1/1343 , G02F1/1333
摘要： An array substrate is provided, including a plurality of pixel unit pairs arranged in an array and defined by mutually intersected gate lines and data lines. Two of the gate lines are arranged between the pixel unit pairs in adjacent rows, each pixel unit pair includes a first pixel unit and a second pixel unit, and a gate insulation layer, a first metal layer, a passivation layer and a pixel electrode layer are stacked on a base substrate and arranged between the first pixel unit and the second pixel unit. Orthographic projections of the pixel electrode layer and the first metal layer onto the base substrate partially overlap to form a storage capacitor, and the first metal layer is connected to a common electrode layer of each pixel unit pair in a lap joint manner.
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公开(公告)号：US20190043897A1
公开(公告)日：2019-02-07
申请号：US16023840
申请日：2018-06-29
发明人： Maokun TIAN , Wei SHEN , Zhonghao HUANG , Zhaojun WANG , Dalong MAO
IPC分类号： H01L27/12
摘要： The present disclosure describes a method for fabricating an array substrate, an array substrate, and a display device. The method includes the following steps: forming a gate electrode on a substrate; forming a gate insulating layer on a side of the gate electrode distal to the substrate; and forming an active layer and a source-drain metal sequentially on a side of the gate insulating layer distal to the gate electrode; forming a protection layer for the source-drain metal on a side of the source-drain metal distal to the gate insulating layer; and etching portion of the source-drain metal corresponding to the channel region to form a source electrode and a drain electrode.
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