TEST KEY TRANSISTOR FOR DEEP TRENCH ISOLATION DEPTH DETECTION

    公开(公告)号:US20240071846A1

    公开(公告)日:2024-02-29

    申请号:US17897725

    申请日:2022-08-29

    CPC classification number: H01L22/34 G01R31/2621 H01L27/1463

    Abstract: This application describes systems and methods for detecting depth in deep trench isolation with semiconductor devices using test key transistors. An example semiconductor device comprises a test key transistor comprising a source, a drain, a channel connected to the source and the drain, and a gate; and a deep trench isolation encroaching into the channel of the test key transistor, wherein: the test key transistor is associated with a specification including a preset gate voltage, a preset source-drain voltage difference, and a predetermined current, and the test key transistor is configured to generate a current within a threshold difference from the predetermined current in the channel in response to receiving the preset gate voltage at the gate and the preset source-drain voltage difference at the source and the drain, and the deep trench isolation encroaches into the channel at a preset depth.

    CENTRALLY SYMMETRIC VERTICAL TRANSFER GATE
    2.
    发明公开

    公开(公告)号:US20240072094A1

    公开(公告)日:2024-02-29

    申请号:US17897975

    申请日:2022-08-29

    CPC classification number: H01L27/14643 H01L27/14603 H01L27/14689

    Abstract: This application describes systems and methods related to vertical transfer gates. An example system includes a photodiode region disposed in a substrate, wherein: the photodiode region is configured to accumulate charge photogenerated in the photodiode region in response to incoming light, the photodiode region comprises a top surface and a bottom surface, the top surface being smaller than the bottom surface, the photodiode region comprises at least two doping concentrations, and a first doping concentration of the two doping concentrations that is closer to the top surface is higher than a second doping concentration of the two doping concentrations that is closer to the bottom surface; and a vertical transfer gate in the substrate, wherein: the vertical transfer gate is above the top surface of the photodiode region and is centrally symmetric to the top surface of the photodiode region, and the vertical transfer gate is configured to transfer the photogenerated charge from the photodiode region to a transfer gate.

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