公开(公告)号：US20250038944A1

公开(公告)日：2025-01-30

申请号：US18227799

申请日：2023-07-28

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： YU LIAO ,  JUNQING SUN

IPC: H04L7/00

Abstract: Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

公开(公告)号：US20240388312A1

公开(公告)日：2024-11-21

申请号：US18198636

申请日：2023-05-17

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： CHANG SHU ,  YU LIAO ,  JUNQING SUN

IPC: H03M13/11 ,  H03M13/15

Abstract: An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.