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公开(公告)号：US3587066A
公开(公告)日：1971-06-22
申请号：US3587066D
申请日：1968-03-26
Applicant: CSF
Inventor： GIBACIER DANIEL , KHAI TRAN VAN
CPC classification number: G11C11/06085
Abstract: A memory arrangement of the matrix type having associated readout and write-in circuits, the readout circuits being designed to provide readout pulses having the same polarity as to write-in pulses so as not to destroy the information contained in each memory element.
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