公开(公告)号：US3587066A

公开(公告)日：1971-06-22

申请号：US3587066D

申请日：1968-03-26

Applicant: CSF

Inventor： GIBACIER DANIEL ,  KHAI TRAN VAN

IPC: G11C7/02 ,  G11C11/06 ,  G11C5/02 ,  G11C7/00

CPC classification number: G11C11/06085

Abstract: A memory arrangement of the matrix type having associated readout and write-in circuits, the readout circuits being designed to provide readout pulses having the same polarity as to write-in pulses so as not to destroy the information contained in each memory element.

公开(公告)号：US3498764A

公开(公告)日：1970-03-03

申请号：US3498764D

申请日：1966-03-28

Applicant: CSF

Inventor： KHAI TRAN VAN

IPC: G11C11/06 ,  H01F1/03 ,  H01F10/06 ,  H01F7/06 ,  G11B5/00

CPC classification number: H01F10/06 ,  G11C11/06085 ,  H01F1/0315 ,  Y10T29/49069 ,  Y10T428/12396 ,  Y10T428/12597