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公开(公告)号：US3700806A
公开(公告)日：1972-10-24
申请号：US3700806D
申请日：1967-09-18
Applicant: CSF
Inventor： VASSEUR JEAN-PIERRE
CPC classification number: G06F7/584 , G06F2207/581 , H04L9/0662
Abstract: In a digital key generator, comprising a network of counters triggered by a clock, and feeding a logical circuit having a plurality of outputs supplying the digits of a quasi-random member, at least some of those outputs respectively feed corresponding shift-register converters whose outputs are substituted for the corresponding outputs of the logical circuit, in order to improve the quasi-random nature of the number delivered by the logical circuit.
Abstract translation: 在数字密钥生成器中，包括由时钟触发的计数器网络，以及馈送具有提供准随机成员的数字的多个输出的逻辑电路，所述输出中的至少一些分别馈送相应的移位寄存器转换器， 为了提高由逻辑电路传递的数量的准随机性质，输出用逻辑电路的相应输出代替。
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公开(公告)号：US3521081A
公开(公告)日：1970-07-21
申请号：US3521081D
申请日：1966-11-30
Applicant: CSF
Inventor： VASSEUR JEAN-PIERRE , SEV ALEXANDRE
IPC: H03K19/0944 , H03K19/096 , H03K19/08
CPC classification number: H03K19/09441 , H03K19/096
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