公开(公告)号：US11502194B2

公开(公告)日：2022-11-15

申请号：US17263207

申请日：2019-07-25

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tse-huang Lo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.