公开(公告)号：US12061857B1

公开(公告)日：2024-08-13

申请号：US17829099

申请日：2022-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  Charles Jay Alpert ,  Andrew Hall

IPC: G06F30/396 ,  G06F1/10 ,  G06F119/12

CPC classification number: G06F30/396 ,  G06F1/10 ,  G06F2119/12

Abstract: Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.