公开(公告)号：US10796049B1

公开(公告)日：2020-10-06

申请号：US16228481

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： Kwangsoo Han ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50 ,  G06F30/3312 ,  G06F30/337 ,  G06F111/10 ,  G06F119/12 ,  G06F30/30

Abstract: Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

公开(公告)号：US10380287B1

公开(公告)日：2019-08-13

申请号：US15638048

申请日：2017-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Dirk Meyer ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Electronic design automation systems, methods, and media are presented for modifying a balanced clock structure. One embodiment involves accessing a circuit design comprising an H-tree clock distribution network that provides a clock signal to a plurality of sinks. Timing requirements for each sink are identified, and a plurality of early tapoff candidate locations are also identified. A corresponding arrival time adjustment associated with each early tapoff candidate location is estimated for early sinks, and an early tapoff location is selected for each early sink based on the early arrival timing requirement and the arrival time adjustment associated with the tapoff location. In various embodiments, different criteria may be used for selecting the early tapoff location, and updated circuit designs are then generated with a route from early sinks to the early tapoff location selected for each early sink.

公开(公告)号：US10318693B1

公开(公告)日：2019-06-11

申请号：US15690043

申请日：2017-08-29

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Zhuo Li ,  Charles Jay Alpert ,  William Robert Reece ,  Thomas Andrew Newton

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.

公开(公告)号：US10102328B1

公开(公告)日：2018-10-16

申请号：US15060020

申请日：2016-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Jay Alpert ,  Mehmet Can Yildiz

IPC: G06F17/50

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

公开(公告)号：US10402522B1

公开(公告)日：2019-09-03

申请号：US15692637

申请日：2017-08-31

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Charles Jay Alpert ,  Thomas Andrew Newton ,  William Robert Reece

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.

公开(公告)号：US12061857B1

公开(公告)日：2024-08-13

申请号：US17829099

申请日：2022-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  Charles Jay Alpert ,  Andrew Hall

IPC: G06F30/396 ,  G06F1/10 ,  G06F119/12

CPC classification number: G06F30/396 ,  G06F1/10 ,  G06F2119/12

Abstract: Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.

公开(公告)号：US10354040B1

公开(公告)日：2019-07-16

申请号：US15676767

申请日：2017-08-14

Applicant: Cadence Design Systems, Inc.

Inventor： Amin Farshidi ,  Thomas Andrew Newton ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50 ,  G06F1/324 ,  G06F1/3296

Abstract: Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.

公开(公告)号：US10289775B1

公开(公告)日：2019-05-14

申请号：US15694309

申请日：2017-09-01

Applicant: Cadence Design Systems, Inc.

Inventor： Brian Wilson ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.

公开(公告)号：US10579767B1

公开(公告)日：2020-03-03

申请号：US15640999

申请日：2017-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Gracieli Posser ,  Charles Jay Alpert ,  Ruth Patricia Jackson

IPC: G06F17/50

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

公开(公告)号：US10460065B1

公开(公告)日：2019-10-29

申请号：US15649426

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li ,  Charles Jay Alpert

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.