公开(公告)号：US11810633B2

公开(公告)日：2023-11-07

申请号：US17460701

申请日：2021-08-30

Applicant: Cadence Design Systems, Inc.

Inventor： Ashwin S. M. ,  Anirudha Shelke ,  Navin Kumar Mishra ,  Phalguni Bala ,  Younus Syed ,  Kiran Baby ,  Sudhir Kumar Katla Shetty

IPC: G11C7/10 ,  G11C29/36 ,  G11C7/22 ,  G11C29/50

CPC classification number: G11C29/36 ,  G11C7/22 ,  G11C29/50004 ,  G11C2207/2254

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.