公开(公告)号：US09071256B1

公开(公告)日：2015-06-30

申请号：US14311648

申请日：2014-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Loren Blair Reiss ,  Chris Moscone ,  Benjamin Louis Heilmann ,  Randall Smith

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.

Abstract translation: 本公开涉及一种与串行器/解串器一起使用的方法，包括： 该方法可以包括将与集成电路（IC）相关联的一个或多个通道模块组合在一起以形成链路，其中一个或多个通道模块中的每一个包括复位状态机和高速复位发生器。 该方法还可以包括提供具有公共复位释放状态机和复位释放同步器和脉冲发生器的公共模块，所述公共模块和一个或多个通道模块被配置为在它们之间通信。 该方法还可以包括使用一个或多个车道模块独立地重置每个链路。