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公开(公告)号：US09071256B1
公开(公告)日：2015-06-30
申请号：US14311648
申请日：2014-06-23
Applicant: Cadence Design Systems, Inc.
Inventor： Loren Blair Reiss , Chris Moscone , Benjamin Louis Heilmann , Randall Smith
IPC: H03M9/00
CPC classification number: H03M9/00
Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.
Abstract translation: 本公开涉及一种与串行器/解串器一起使用的方法，包括： 该方法可以包括将与集成电路（IC）相关联的一个或多个通道模块组合在一起以形成链路，其中一个或多个通道模块中的每一个包括复位状态机和高速复位发生器。 该方法还可以包括提供具有公共复位释放状态机和复位释放同步器和脉冲发生器的公共模块，所述公共模块和一个或多个通道模块被配置为在它们之间通信。 该方法还可以包括使用一个或多个车道模块独立地重置每个链路。
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公开(公告)号：US10069656B1
公开(公告)日：2018-09-04
申请号：US15441687
申请日：2017-02-24
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren Blair Reiss
Abstract: Systems and methods disclosed herein provide for preventing the mis-equalization of signals transmitted over short transmission channels. Embodiments of the systems and methods provide for a receiver including a digital receiver equalization circuit that selectively provides a correction signal to a DFE tap weight based on the value of the current DFE tap weight as well as the logical values of the in-phase and error data samples associated with received signal.
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公开(公告)号：US09940288B1
公开(公告)日：2018-04-10
申请号：US14948761
申请日：2015-11-23
Applicant: Cadence Design Systems, Inc.
Inventor： Loren Blair Reiss , Fred Staples Stivers , Scott Gerald Bare
CPC classification number: G06F13/4068 , G06F13/20 , H04L7/033 , H04L7/04
Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more enqueue pointers and dequeue pointers.
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公开(公告)号：US09998303B1
公开(公告)日：2018-06-12
申请号：US15380474
申请日：2016-12-15
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren Blair Reiss
CPC classification number: H04L25/03057 , H04B1/16
Abstract: A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal to a threshold value. An error signal sample is correlated with at least one delayed data signal sample to determine whether to adjust a control coefficient of the equalizer. Thus the equalizer is controlled as if the DFE had at least one additional tap.
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