公开(公告)号：US11592482B1

公开(公告)日：2023-02-28

申请号：US17204334

申请日：2021-03-17

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Anil Malik ,  Bharath Nandakumar

IPC: G01R31/3177 ,  G01R31/317

Abstract: Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions (“0” to “0”, “0” to “1”, “1” to 0”, “1” to “1”) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.