公开(公告)号：US09400311B1

公开(公告)日：2016-07-26

申请号：US14675365

申请日：2015-03-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Anil Malik ,  Sameer Chakravarthy Chillarige ,  Sharjinder Singh ,  Joseph Swenton ,  Gilbert Vandling

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318342 ,  G01R31/31703

Abstract: In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

Abstract translation: 为了检测和定位共享共同设计的多个芯片或其他电路中的缺陷或故障，每个芯片都响应于输入而被测试不正确的输出或失败。 然后通过在芯片设计的仿真芯片上模拟一系列可疑故障候选，然后将每个故障候选产生的不正确输出与各个芯片的不正确输出进行比较，确定不正确的输出在单个仿真中进行统一诊断，以确定 如果故障候选者产生芯片的所有故障，而不产生其他故障。 测试输入和预期输出可以通过自动测试模式生成来预先确定。 故障候选可以通过使用诸如后锥跟踪的回溯处理来确定。 可能与测量点，导致故障的输入模式和故障值相关联地记录故障。

公开(公告)号：US11592482B1

公开(公告)日：2023-02-28

申请号：US17204334

申请日：2021-03-17

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Anil Malik ,  Bharath Nandakumar

IPC: G01R31/3177 ,  G01R31/317

Abstract: Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions (“0” to “0”, “0” to “1”, “1” to 0”, “1” to “1”) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.

公开(公告)号：US10180457B1

公开(公告)日：2019-01-15

申请号：US15062013

申请日：2016-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Sharjinder Singh ,  Anil Malik ,  Joseph Michael Swenton

IPC: G01R31/317 ,  G01R31/3177 ,  G06F17/50 ,  G01R31/00 ,  G01R31/311

Abstract: The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

公开(公告)号：US10996270B1

公开(公告)日：2021-05-04

申请号：US16128177

申请日：2018-09-11

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sameer Chillarige ,  Joe Swenton ,  Anil Malik ,  Krishna Chakravadhanula

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/00 ,  G06F16/28 ,  G01R31/3183

Abstract: Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at least one previously diagnosed electronic device, that the wherein the processor diagnoses defects in one or more of the plurality of electronic devices using the grouped failure data, and that the processor outputs the diagnosis results to the diagnosis results database.

公开(公告)号：US10338137B1

公开(公告)日：2019-07-02

申请号：US15215261

申请日：2016-07-20

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Anil Malik ,  Sharjinder Singh ,  Joseph Michael Swenton

IPC: G01R31/3183 ,  G01R31/3181 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3193

Abstract: A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

公开(公告)号：US09864004B1

公开(公告)日：2018-01-09

申请号：US15073001

申请日：2016-03-17

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Brion L. Keller ,  Joseph Michael Swenton ,  Sharjinder Singh ,  Anil Malik

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31703 ,  G01R31/31908 ,  G06F11/00

Abstract: Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary output pins. Embodiments may include performing fault selection on a single core instance for each failure associated with the plurality of core instances and performing fault simulations on the single core instance for each candidate faults associated with the plurality of core instances. Embodiments may include generating fault signatures for each detected fault based upon the instances associated with each detected fault and analyzing each fault signature to determine failure locations.