公开(公告)号：US10204201B1

公开(公告)日：2019-02-12

申请号：US15199059

申请日：2016-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Lawrence Loh ,  Artur Melo Mota Costa ,  Breno Rodrigues Guimaraes ,  Fabiano Peixoto ,  Andrea Iabrudi Tavares

IPC: G06F17/50

Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.