公开(公告)号：US09633151B1

公开(公告)日：2017-04-25

申请号：US14675699

申请日：2015-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Xiaoyang Sun ,  Marcus Vinicius da Mata Gomes ,  Andrea Iabrudi Tavares ,  Lawrence Loh ,  Fabiano Peixoto

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5031 ,  G06F2217/62

Abstract: Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.

公开(公告)号：US10204201B1

公开(公告)日：2019-02-12

申请号：US15199059

申请日：2016-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Lawrence Loh ,  Artur Melo Mota Costa ,  Breno Rodrigues Guimaraes ,  Fabiano Peixoto ,  Andrea Iabrudi Tavares

IPC: G06F17/50

Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

公开(公告)号：US09922209B1

公开(公告)日：2018-03-20

申请号：US15269919

申请日：2016-09-19

Applicant: Cadence Design Systems, Inc.

Inventor： Victor Markus Purri ,  Caio Araújo Teixeira Campos ,  Magnus Björk ,  Lawrence Loh ,  Claudionor Jose Nunes Coelho

IPC: G06F17/50 ,  G06F11/22 ,  G06F21/71

CPC classification number: G06F21/71 ,  G06F17/5022 ,  G06F17/5045 ,  G06F21/76

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

公开(公告)号：US09934410B1

公开(公告)日：2018-04-03

申请号：US15269931

申请日：2016-09-19

Applicant: Cadence Design Systems, Inc.

Inventor： Victor Markus Purri ,  Caio Araújo Teixeira Campos ,  Magnus Björk ,  Lawrence Loh ,  Claudionor Jose Nunes Coelho

IPC: G06F11/22 ,  G06F17/50 ,  G06F21/71

CPC classification number: G06F21/71 ,  G06F17/5022 ,  G06F17/5045 ,  G06F21/76

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.