公开(公告)号：US09858372B1

公开(公告)日：2018-01-02

申请号：US15169660

申请日：2016-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Hudson Dyele Oliveira ,  Abner Luis Panho Marciano ,  Guilherme Seminotti Braga ,  Caio Texeira Campos ,  Breno Rodrigues Guimares ,  Rodrigo Fonseca Rocha Soares ,  Laiz Lipiainen Santos ,  Raquel Lara dos Santos Pereira ,  Adriana Cassia Rossi de Almeida Braz

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5045

Abstract: Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.