公开(公告)号：US10540467B1

公开(公告)日：2020-01-21

申请号：US15943819

申请日：2018-04-03

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Abner Luis Panho Marciano ,  Matheus Nogueira Fonseca ,  Ronalu Augusta Nunes Barcelos ,  Fabiano Cruz Peixoto

IPC: G06F17/50

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

公开(公告)号：US10796051B1

公开(公告)日：2020-10-06

申请号：US16399536

申请日：2019-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Abner Luis Panho Marciano ,  Matheus Fonseca ,  Thamara Karen Cunha Andrade ,  Raquel Lara dos Santos Pereira ,  Fabiano Cruz Peixoto ,  Rodolfo Santos Teixeira ,  Rafael Gontijo Hamdan ,  Bruno Andrade Pereira

IPC: G06F30/00 ,  G06F30/3323 ,  G06F30/3312 ,  G06F111/04 ,  G06F111/20

Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.

公开(公告)号：US09858372B1

公开(公告)日：2018-01-02

申请号：US15169660

申请日：2016-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Hudson Dyele Oliveira ,  Abner Luis Panho Marciano ,  Guilherme Seminotti Braga ,  Caio Texeira Campos ,  Breno Rodrigues Guimares ,  Rodrigo Fonseca Rocha Soares ,  Laiz Lipiainen Santos ,  Raquel Lara dos Santos Pereira ,  Adriana Cassia Rossi de Almeida Braz

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5045

Abstract: Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.

公开(公告)号：US09665682B1

公开(公告)日：2017-05-30

申请号：US14871847

申请日：2015-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Breno Rodrigues Guimarães ,  Abner Luis Panho Marciano ,  Fabiano Peixoto

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/504

Abstract: Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an original next counter value based at least in part on a set of critical values. The counter is accelerated from the current counter value to the engine synthesized next counter value when the counter abstraction module determines to accelerate the counter.